AD7766-1 AD [Analog Devices], AD7766-1 Datasheet - Page 5

• Manufacturer Part Number: AD7766-1
• Description: 24-Bit, 8.5 mW, 109 dB, 128/64/32 kSPS ADCs
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
AV
unless otherwise noted
Table 3.
Parameter
DRDY Operation
Read Operation
Read Operation with CS Low
Daisy Chain Operation
SYNC/PD Operation
1
2
3
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
t
MCLK frequency is 1.024 MHz.
n = 1 for AD7767, n = 2 for the AD7767-1, n = 4 for the AD7767-2.
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
and t
t
DD
1
2
3
4
5
READ
6
7
8
9
10
11
SCLK
12
13
14
15
16
17
18
19
20
21
SETTLING
DRDY
2
= DV
3
3
3
allow a ~90% to 10% duty cycle to be used for the MCLK input where the minimum is 10% for the clock high time and 90% for MCLK low time. The maximum
3
DD
= 2.5 V ± 5%, V
1
DRIVE
Limit at T
510
100
900
265
128
71
294
435
492
n × 8 × t
0
6
60
50
25
24
10
10
10
1/t
6
0
0
0
1
2
1
20
1
510
592 × (n + 2)
t
DRDY
8
= 1.7 V to 3.6 V, V
− t
MCLK
5
MIN
, T
MAX
Unit
ns typ
ns min
ns max
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns typ
ns min
ns max
ns max
ns max
ns max
ns max
ns min
ns min
ns min
min
ns max
ns min
ns min
ns max
ns min
ns max
ns typ
ns typ
ns min
ns typ
t
REF
MCLK
= 5 V, common-mode input = V
Rev. 0 | Page 5 of 24
Description
MCLK rising edge to DRDY falling edge
MCLK high pulse width
MCLK low pulse width
MCLK rising edge to DRDY rising edge (AD7767)
MCLK rising edge to DRDY rising edge (AD7767-1)
MCLK rising edge to DRDY rising edge (AD7767-2)
DRDY pulse width (AD7767)
DRDY pulse width (AD7767-1)
DRDY pulse width (AD7767-2)
DRDY low period, read data during this period
DRDY period
DRDY falling edge to CS setup time
CS falling edge to SDO three-state disabled
Data access time after SCLK falling edge (V
Data access time after SCLK falling edge (V
Data access time after SCLK falling edge (V
Data access time after SCLK falling edge (V
SCLK falling edge to data valid hold time (V
SCLK high pulse width
SCLK low pulse width
Minimum SCLK period
Bus relinquish time after CS rising edge
CS rising edge to DRDY rising edge
DRDY falling edge to data valid setup time
DRDY rising edge to data valid hold time
SDI valid to SCLK falling edge setup time
SCLK falling edge to SDI valid hold time
SYNC/PD falling edge to MCLK rising edge
MCLK rising edge to DRDY rising edge going into SYNC/PD
SYNC/PD rising edge to MCLK rising edge
MCLK rising edge to DRDY falling edge coming out of SYNC/PD
Filter settling time after a reset or power-down
REF
/2, T
A
= −40°C (T
DD
DRIVE
DRIVE
DRIVE
DRIVE
) and timed from a voltage level of 1.7 V.
DRIVE
= 1.7 V)
= 2.3 V)
= 2.7 V)
= 3.0 V)
MIN
= 3.6 V)
) to +105°C (T
AD7767
MAX
),