AD5532-3 AD [Analog Devices], AD5532-3 Datasheet - Page 4

• Manufacturer Part Number: AD5532-3
• Description: 32-Channel, 14-Bit Voltage-Output DAC
• Manufacturer: AD [Analog Devices]

TIMING CHARACTERISTICS
PARALLEL INTERFACE
Parameter
t
t
t
t
t
t
NOTES
1
2
Specifications subject to change without notice.
SERIAL INTERFACE
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
NOTES
1
2
3
4
Specifications subject to change without notice.
PARALLEL INTERFACE TIMING DIAGRAMS
AD5532
See Interface Timing Diagram.
Guaranteed by design and characterization, not production tested.
See Serial Interface Timing Diagrams.
Guaranteed by design and characterization, not production tested.
In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.
These numbers are measured with the load circuit of Figure 2.
1
2
3
4
5
6
CLKIN
1
2
3
4
5
6
7
8
9
10
11
4
4
A4–A0, CAL,
OFFS SEL
3
WR
CS
1, 2
1, 2
Limit at T
(A Version)
0
0
50
50
20
0
Limit at T
(A Version)
14
28
28
10
50
10
5
5
20
60
400
400
MIN
MIN
, T
, T
MAX
MAX
Unit
ns min
ns min
ns min
ns min
ns min
ns min
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
Conditions/Comments
CS to WR Setup Time
CS to WR Hold Time
CS Pulsewidth Low
WR Pulsewidth Low
A4–A0, CAL, OFFS_SEL to WR Setup Time
A4–A0, CAL, OFFS_SEL to WR Hold Time
Conditions/Comments
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
D
D
SYNC Falling Edge to SCLK Rising Edge Setup Time
SCLK Rising Edge to D
SCLK Falling Edge to D
10th SCLK Falling Edge to SYNC Falling Edge for Readback
24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write
IN
IN
Setup Time
Hold Time
OUTPUT
OUT
OUT
PIN
TO
Valid
High Impedance
C
50pF
L
200 A
200 A
I
I
OH
OL
1.6V