AD7291_11 AD [Analog Devices], AD7291_11 Datasheet - Page 21

• Manufacturer Part Number: AD7291_11
• Description: 8-Channel, I2C, 12-Bit SAR ADC with Temperature Sensor
• Manufacturer: AD [Analog Devices]

I
Control of the AD7291 is carried out via the I
serial bus. The AD7291 is connected to this bus as a slave device
under the control of a master device such as the processor.
SERIAL BUS ADDRESS BYTE
The first byte the user writes to the device is the slave address
byte. Similar to all I
7-bit serial address. The three MSBs of this address are set to
010. The four LSBs are user-programmable by the three-state
input pins, AS0 and AS1, as shown in Table 31.
In Table 31, H means tie the pin to V
to GND, and NC refers to a pin left floating. Note that in this
final case, the stray capacitance on the pin must be less than
30 pF to allow correct detection of the floating state; therefore,
any PCB trace must be kept as short as possible.
Table 31. Slave Address Control Using Three-State Input Pins
AS1
H
H
H
NC
NC
NC
L
L
L
GENERAL I
Figure 24 shows the timing diagram for general read and write
operations using an I
When no device is driving the bus, both SCL and SDA are high.
This is known as the idle state. When the bus is idle, the master
initiates a data transfer by establishing a start condition, defined
as a high-to-low transition on the serial data line (SDA) while
2
C INTERFACE
SDA
SCL
START COND
BY MASTER
AS0
H
NC
L
H
NC
L
H
NC
L
2
C TIMING
2
C-compatible devices, the AD7291 has a
A6
2
C-compliant interface.
Binary
010 0000
010 0010
010 0011
010 1000
010 1010
010 1011
010 1100
010 1110
010 1111
A5
SLAVE ADDRESS BYTE
Slave Address (A6 to A0)
USER PROGRAMMABLE 5 LSBs
A4
DRIVE
A3
, L means tie the pin
A2
2
C compatible
A1
Hex
0x20
0x22
0x23
0x28
0x2A
0x2B
0x2C
0x2E
0x2F
A0
Figure 24. General I
R/W
ACK. BY
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AD7291
P7
2
the serial clock line (SCL) remains high. This indicates that a
data stream follows. The master device is responsible for
generating the clock.
Data is sent over the serial bus in groups of nine bits—eight bits
of data from the transmitter followed by an acknowledge bit
(ACK) from the receiver. Data transitions on the SDA line must
occur during the low period of the clock signal and remain
stable during the high period. The receiver should pull the SDA
line low during the acknowledge bit to signal that the preceding
byte has been received correctly. If this is not the case, cancel
the transaction.
The first byte that the master sends must consist of a 7-bit slave
address, followed by a data direction bit. Each device on the
bus has a unique slave address; therefore, the first byte sets up
communication with a single slave device for the duration of the
transaction.
The transaction can be used either to write to a slave device
(data direction bit = 0) or to read data from it (data direction
bit = 1). In the case of a read transaction, it is often necessary
first to write to the slave device (in a separate write transaction)
to tell it from which register to read. Reading and writing
cannot be combined in one transaction.
When the transaction is complete, the master can keep control
of the bus, initiating a new transaction by generating another
start bit (high-to-low transition on SDA while SCL is high).
This is known as a repeated start (SR). Alternatively, the bus
can be relinquished by releasing the SCL line followed by the
SDA line. This low-to-high transition on SDA while SCL is high
is known as a stop bit (P), and it leaves the I
state (no current is consumed by the bus).
The example in Figure 24 shows a simple write transaction
with an AD7291 as the slave device. In this example, the
AD7291 register pointer is being set up for a future read
transaction.
C Timing
P6
P5
REGISTER ADDRESS
P4
P3
P2
P1
P0
ACK. BY
AD7291
2
C bus in its idle
STOP BY
MASTER
AD7291