X9448WP24 INTERSIL [Intersil Corporation], X9448WP24 Datasheet - Page 2

• Manufacturer Part Number: X9448WP24
• Description: Mixed Signal with 2-Wire Interface
• Manufacturer: INTERSIL [Intersil Corporation]

PIN DESCRIPTIONS
Host Interface Pins
Serial Clock (SCL)
The SCL input is used to clock data into and out of the
X9448.
Serial Data (SDA)
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs. An open drain output requires
the use of a pull-up resistor. For selecting typical val-
ues, refer to the guidelines for calculating typical val-
ues on the bus pull-up resistors graph.
Device Address (A
The address inputs are used to set the least significant
4 bits of the 8-bit slave address. A match in the slave
address serial data stream must be made with the
address input in order to initiate communication with
the X9448. A maximum of 16 devices may share the
same 2-wire serial bus.
Potentiometer Pins
V
The V
nections on either end of a mechanical potentiometer.
V
The wiper output is equivalent to the wiper output of a
mechanical potentiometer and is connected to the
inverting input of the voltage comparator.
Comparator and Device Pins
Voltage Input V
V
inverting) inputs of the two comparators.
Buffered Voltage Outputs V
The V
comparator outputs enabled by respective bits in the
volatile analog control register.
H
W
NI0
(V
(V
and V
H0
H
W0
OUT0
and V
- V
- V
NI1
H1
, and V
W1
L
), V
are the input voltages to the plus (non-
)
inputs are equivalent to the terminal con-
NI0
L
(V
, V
0
OUT1
L0
- A
NI1
- V
3
)
L1
2
are the buffered voltage
)
OUT0
, V
OUT1
X9448
Hardware Write Protect Input WP
The WP pin when low prevents nonvolatile writes to
the wiper counter and analog control registers.
Analog Supplies V+, V-
The analog supplies V+, V- are the supply voltages for
the XDCP analog section and the voltage comparators.
System Supply V
The system supply V
to bias the interface and control circuits.
PIN CONFIGURATION
V
OUT1
SDA
V
V
SCL
SDA
V
V
V
V
V
V
V
V
V
V
WP
V
NC
NI1
W1
A
SS
A
CC
W0
A1
W1
H1
L1
V-
H0
A
H1
SS
L0
L1
1
3
2
CC
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
11
12
CC
and Ground V
X9448
X9448
TSSOP
and its reference V
SOIC
24
23
22
21
20
19
18
17
16
15
14
24
23
22
21
20
19
18
17
16
15
14
13
13
SS
V+
V
V
NC
A0
NC
A
SCL
NC
V
V
V-
WP
A
V
V
V
V
NC
V+
V
V
A
NC
OUT0
NI0
3
NI1
OUT1
2
W0
H0
L0
CC
OUT0
NI0
0
SS
April 18, 2005
is used
FN8201.0