X9251-2.7 INTERSIL [Intersil Corporation], X9251-2.7 Datasheet - Page 4

• Manufacturer Part Number: X9251-2.7
• Description: Single Supply/Low Power/256-Tap/SPI Bus
• Manufacturer: INTERSIL [Intersil Corporation]

PIN DESCRIPTIONS
Bus Interface Pins
S
SO is a serial data output pin. During a read cycle,
data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
S
SI is the serial data input pin. All opcodes, byte
addresses and data to be written to the device
registers are input on this pin. Data is latched by the
rising edge of the serial clock.
S
The SCK input is used to clock data into and out of the
X9251.
H
HOLD is used in conjunction with the CS pin to select
the device. Once the part is selected and a serial
sequence is underway, HOLD may be used to pause
the serial communication with the controller without
resetting the serial sequence. To pause, HOLD must
be brought LOW while SCK is LOW. To resume
communication, HOLD is brought HIGH, again while
SCK is LOW. If the pause feature is not used, HOLD
should be held HIGH at all times.
D
The address inputs are used to set the two least
significant bits of the slave address. A match in the
slave address serial data stream must be made with
the address input in order to initiate communication
with the X9251. Device pins A1 - A0 must be tie to a
logic level which specify the internal address of the
device, see Figures 2, 3, 4, 5 and 6.
C
When CS is HIGH, the X9251 is deselected and the
SO pin is at high impedance, and (unless an internal
write cycle is underway) the device is in the standby
state. CS LOW enables the X9251, placing it in the
active power mode. It should be noted that after a
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
ERIAL
ERIAL
ERIAL
OLD
EVICE
HIP
S
(HOLD)
ELECT
O
I
C
A
NPUT
LOCK
UTPUT
DDRESS
(CS)
(SI)
(SCK)
(SO)
(A1 - A0)
4
X9251
Potentiometer Pins
R
The R
connections on a mechanical potentiometer. Since
there are 4 potentiometers, there are 4 sets of R
R
and so on.
R
The wiper pin are equivalent to the wiper terminal of a
mechanical
potentiometers, there are 4 sets of R
is the terminals of DCP0 and so on.
Supply Pins
S
G
The V
pin is the system ground.
Other Pins
N
No connect pins should be left floating. This pins are
used for Intersil manufacturing and testing purposes.
H
The WP pin when LOW prevents non-volatile writes to
the Data Registers.
PRINCIPLES OF OPERATION
The X9251 is an integrated circuit incorporating four
DCPs and their associated registers and counters,
and a serial interface providing direct communication
between a host and the potentiometers.
DCP Description
Each DCP is implemented with a combination of
resistor elements and CMOS switches. The physical
ends of each DCP are equivalent to the fixed terminals
of a mechanical potentiometer (R
RW pin is an intermediate node, equivalent to the
wiper terminal of a mechanical potentiometer.
The position of the wiper terminal within the DCP is
controlled by an 8-bit volatile Wiper Counter Register
(WCR).
YSTEM
H
L
W
O
ARDWARE
ROUND
, R
such that R
C
ONNECT
L
CC
H
S
and R
(V
pin is the system supply voltage. The V
UPPLY
SS
W
potentiometer.
)
RITE
H0
L
pins are equivalent to the terminal
V
and R
OLTAGE
P
ROTECT
L0
are the terminals of DCP0
(V
I
CC
Since
NPUT
H
)
AND
and R
W
(WP)
there
such that R
S
September 14, 2005
UPPLY
L
pins). The
are
FN8166.2
H
and
W0
SS
4