AD5420BCPZ AD [Analog Devices], AD5420BCPZ Datasheet
AD5420BCPZ
Related parts for AD5420BCPZ
AD5420BCPZ Summary of contents
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... The output is open circuit protected and can drive inductive loads of 1H. The device is specified to operate with a power supply range from 10 40V (AD5420BREZ) or 10.8V to 60V (AD5420BCPZ). Output loop compliance – 2.5 V. The flexible serial interface is SPI and MICROWIRE compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications ...
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AD5420 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 6 Timing Characteristics ................................................................ 7 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 ...
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Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM SELECT AD5420 CLEA R INPUT SHIFT LATCH REGISTER SCLK AND SDIN CONTROL SDO LOGIC POWER ON RESET DGND* *LFCSP Package CAP1 CC 16 16-BIT / DAC VREF REFIN REFOUT Figure 1. ...
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AD5420 SPECIFICATIONS 10.8V to 40V/60V , AGND = DGND = 0 V, REFIN external all specifications range unless otherwise noted. MIN MAX Table 2. Parameter ...
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... Output Voltage Output Load Current Short Circuit Current Power Dissipation 1 Maximum supply for the AD5420BREZ is 40V, Maximum supply for the AD5420BCPZ is 60V 2 Temperature range: -40°C to +85°C; typical at +25°C. 3 Guaranteed by design and characterization, not production tested. 2 Value Unit 0.4 ...
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... MIN MAX Table 3. 2 Parameter DYNAMIC PERFORMANCE Output Current Settling Time 1 Maximum supply for the AD5420BREZ is 40V, Maximum supply for the AD5420BCPZ is 60V 2 Guaranteed by design and characterization, not production tested Unit Test Conditions/Comments TBD µs typ To 0 ...
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... Maximum supply for the AD5420BREZ is 40V, Maximum supply for the AD5420BCPZ is 60V 2 Guaranteed by characterization. Not production tested. 3 All input signals are specified with (10 See Figure 2, Figure 3, and Figure Capacitive load on SDO output ...
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AD5420 SCLK LATCH SDIN CLEAR OUTPUT SCLK LATCH SDIN DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DATA SCLK 1 2 LATCH SDIN DB23 INPUT WORD FOR DAC ...
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Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Transient currents 100 mA do not cause SCR latch-up. Table 5. Parameter Rating AV to AGND, DGND −0.3V to 60V AGND, ...
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Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS GND AD5420 FAULT 3 GND 4 GND 5 TOP VIEW CLEAR 6 (Not to Scale) LATCH 7 SCLK 8 SDIN 9 SDO 10 AGND 11 GND 12 Figure ...
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Preliminary Technical Data TSSOP Pin No. LFCSP Pin No. Mnemonic Paddle Paddle AGND Description Ground reference for analog circuitry. Rev. PrD | Page AD5420 ...
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AD5420 TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. Integral Non Linearity vs. Code Figure 8.Differential Non Linearity vs. Code Figure 9. Total Unadjusted Error vs. Code Preliminary Technical Data Figure 10. Integral Non Linearity vs. Temperature Figure 11. Differential Non Linearity vs. ...
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Preliminary Technical Data Figure 13. Differential Non Linearity vs. Supply Voltage Figure 14. Integral Non Linearity vs. Reference Voltage Figure 15. Differential Non Linearity vs. Reference Voltage Figure 16. Total Unadjusted Error vs. Reference Voltage Figure 17. Total Unadjusted Error ...
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AD5420 Figure 19. Gain Error vs. Temperature Figure 20. Voltage Compliance vs. Temperature Figure 23. DI vs.Logic Input Voltage CC Preliminary Technical Data Figure 21. I Figure 22. I OUT Figure 24. AI Rev. PrD | Page ...
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Preliminary Technical Data Figure 25. DV Output Voltage vs Figure 26. Refout Turn-on Transient Figure 27. Refout Output Noise (0.1Hz to 10Hz Bandwidth) Load Current CC Rev. PrD | Page Figure 28. Refout Output Noise ...
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AD5420 Figure 31. Refout Histogram of Thermal Hysteresis Preliminary Technical Data Figure 32. Refout Voltage vs. Load Current Rev. PrD | Page ...
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Preliminary Technical Data TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer ...
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AD5420 THEORY OF OPERATION The AD5420 is a precision digital to current loop output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating current loop ...
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Preliminary Technical Data Table 7. Input Shift Register Format MSB D23 D22 D21 D20 D19 D18 D17 ADDRESS WORD Table 8. Control Word Functions Address Function Word 00000000 No Operation (NOP) 00000001 DATA Register 00000010 Readback register value as per ...
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AD5420 Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy chain several devices together as shown in Figure 35. This daisy-chain mode can be useful in system diagnostics and in reducing the number ...
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Preliminary Technical Data DEFAULT CONFIGURATION On initial power-up of the AD5420, the power-on-reset circuit ensures that all registers are loaded with zero-code, as such the default output range is 4mA to 20mA. The current output until a value is programmed ...
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AD5420 RESET REGISTER The RESET register is addressed by setting the control word of the input shift register to 0x56. The data to be written to the RESET register is entered in positions D15 shown in Table ...
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Preliminary Technical Data FEATURES FAULT ALERT The AD5420 is equipped with a FAULT pin, this is an open- drain output allowing several AD5420 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is ...
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AD5420 DIGITAL SLEW RATE CONTROL The Slew Rate Control feature of the AD5420 allows the user to control the rate at which the output current changes. With the slew rate control feature disabled the output currrent will change at a ...
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Preliminary Technical Data APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads connect a 0.01µF capacitor between I and GND. This will ensure OUT stability with loads beyond 50mH. There is no maximum capacitance limit. The capacitive ...
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... AI directly to ground. At maximum ambient temperature of 85°C the AD5420BREZ (24-lead TSSOP) can dissipate 950mW and the AD5420BCPZ (40-lead LFCSP) can dissipate 1.42W. To ensure the junction temperature does not exceed 125°C while driving the maximum current of 24mA directly into ...
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... PLANE 0.10 COPLANARITY Figure 42. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] 6.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model AV max DD AD5420BREZ 40V AD5420BCPZ 60V 13 4.50 4.40 4.30 6.40 BSC 12 1.05 1.00 8° 0.80 0° 0.20 0.30 0.09 0.19 COMPLIANT TO JEDEC STANDARDS MO-153-ADT (RE-24) Dimensions shown in millimeters 0.60 MAX 0.50 BSC 5 ...
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AD5420 NOTES Preliminary Technical Data Rev. PrD | Page ...
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Preliminary Technical Data NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06997-0-11/07(PrD) Rev. PrD | Page AD5420 ...