ISL70002SEH INTERSIL [Intersil Corporation], ISL70002SEH Datasheet
ISL70002SEH
Related parts for ISL70002SEH
ISL70002SEH Summary of contents
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... Two ISL70002SEH devices can be synchronized 180° out-of-phase to reduce input RMS ripple current. High integration makes the ISL70002SEH an ideal choice to power small form factor applications. Two devices can be synchronized to provide a complete power solution for large scale digital ICs, like field programmable gate arrays (FPGAs), that require separate core and I/O voltages ...
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... These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. For Moisture Sensitivity Level (MSL), please see device information page for ISL70002SEH. For more information on MSL please see techbrief TB363. 2 ...
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... Slave’s redundant A/B/C error amp output current. If using current share, tie ISHA/B/C of the Master to ISHA/B/C of the Slave. If not using current share, tie ISHA/B/C to DVDD. ISHA/B/C are tri-stated prior to a valid POR and when ISHEN = DGND. 3 ISL70002SEH ISL70002SEH (64 LD CQFP) TOP VIEW ...
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... This pin is a trim input and is used to adjust various internal circuitry. Connect this pin to the PCB ground plane. 21 GND This pin is connected to an internal metal die trace that serves as a sensitive node noise shield. Connect this pin to the PCB ground plane. 4 ISL70002SEH ⋅ ⁄ ...
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... Master PWM circuits. When configured as an input (clock Slave Mode, M/S = DGND), this pin uses the SYNC output from another ISL70002SEH or an external clock to drive the clock Slave PWM circuitry. If synchronizing to an external clock, the clock must be SEE hardened and the frequency must be within the range of 400kHz to 1 ...
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... FB 64 REF 1.5k 0.22µF AVDD 6 ISL70002SEH AVDD 13 PGOOD LX1 24 27 LX2 33 LX3 36 LX4 39 LX5 42 LX6 45 LX7 48 LX8 54 LX9 57 ISL70002SEH LX10 63 OCA 19.6k 62 OCSSA OCB 61 19.6k OCSSB 60 18 TDO 19 TDI 20 TPGM FIGURE 3. SINGLE UNIT OPERATION 1 1 1µF 1µF 1k 10nF 500nH VOUT + 1µF 6x150µF 1.8 1nF 4 ...
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... SC1 51 SC0 59 EN ISL70002SEH 22 SYNC REF DVDD1 DVDD2 29 M/S 30 FSEL 17 PORSEL 52 SC1 51 SC0 59 EN ISL70002SEH 22 SYNC REF FIGURE 4. TWO PHASE OPERATION WITH CURRENT SHARING 1 1 DVDD1 1µF 1µF 13 PGOOD LX1 24 27 LX2 500nH 33 LX3 36 LX4 39 LX5 42 LX6 ...
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... Enabled, Current Share Slave) Standby Supply Current (Current Share Enabled, Current Share Slave) OUTPUT VOLTAGE & CURRENT Reference Voltage 8 ISL70002SEH Thermal Information (Note 3) Thermal Resistance CQFP Package (Notes Operating Junction Temperature Range . . . . . . . . . . . . . -55°C to +150°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Pb-Free Reflow Profile ...
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... Deadtime (Note 12) Efficiency (Note 12) POWER-ON RESET VIN POR Enable (EN) Input Voltage Enable (EN) Input Leakage Current 9 ISL70002SEH Unless otherwise noted AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 5.5V; IN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor -55°C to +125°C; Post 100krad(Si). (Note 6). ...
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... Slave ISHCOM Input Leakage Current Slave ISHCOM Pull-Down Resistance Slave ISHCOM Input High Voltage Slave ISHCOM Input Low Voltage Slave ISHCOM Input Voltage Hysteresis 10 ISL70002SEH Unless otherwise noted AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 5.5V; IN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor -55° ...
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... Tested sequencially on LX2, LX6 and LX9. 14. Tested sequencially on LX2 and LX6 at 535mA to 735mA and 2.3A to 2.6A. 15. Tested in accordance with MIL-STD-883, method 1019, condition A. 11 ISL70002SEH Unless otherwise noted AVDD = DVDD = PVINx = EN = FSEL = M/S = SC0 = SC1 5.5V; IN with a 1kΩ resistor; REF is bypassed to GND with a 220nF capacitor; ...
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... TEMPERATURE (°C) FIGURE 7. OSC FREQUENCY OCx DISABLED -55 -35 - TEMPERATURE (°C) FIGURE 9. SUSTAINED OUTPUT CURRENT WITH OVERCURRENT DISABLED 12 ISL70002SEH 602.0 601.5 601.0 600.5 600.0 599.5 599.0 598.5 598 105 125 65 85 105 125 105 125 ...
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... Typical Performance Curves FIGURE 11. LX ON-RESISTANCE, ALL POWER BLOCKS IN PARALLEL ISL70002SEH (Continued PFET NFET 5 0 -55 -35 - TEMPERATURE (°C) 105 125 = 3V IN FN8264.1 April 5, 2012 ...
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... LX7 PGND7 PVIN6 LX6 PGND6 The output voltage of the ISL70002SEH can be adjusted using an external resistor divider as shown in Figure 13. R selected as 1kΩ to mitigate SEE. R 4.7nF ceramic capacitor, C stability margins. The REF pin should be bypassed to AGND with a 220nF ceramic capacitor to mitigate SEE. It should be noted that no current (sourcing or sinking) is available from the REF pin ...
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... SYNC input of a Master configured regulator SYNC output external clock. Two Phase Operation The ISL70002SEH is capable of operating 2 ICs as a single Two Phase regulator with nearly twice the load current capacity. In this mode, a redundant Current Sharing bus balances the load current between the two devices and communicates any fault conditions ...
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... I SS DVDD DVDD Fault Monitoring and Protection The ISL70002SEH actively monitors output voltage and current to detect fault conditions. Fault conditions trigger protective measures to prevent damage to the regulator and external load device. Undervoltage Protection A hysteretic comparator monitors the FB pin of the regulator. The feedback voltage is compared to an undervoltage threshold that is a fixed percentage of the reference voltage ...
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... The critical load parameters in choosing the output capacitors are the maximum size of the load step (ΔI STEP 17 ISL70002SEH rate (di/dt), and the maximum allowable output voltage deviation under transient loading (ΔV according to their capacitance, ESR (Equivalent Series Resistance) and ESL (Equivalent Series Inductance). ...
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... RMS ripple current required by the circuit. A combination of low ESR tantalum capacitors and ceramic capacitors with X7R dielectric are recommended. The ISL70002SEH requires a minimum effective input capacitance of 100µF for stable operation. PCB Design PCB design is critical to high-frequency switching regulator performance ...
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... Substrate and Metal Lid PGND ADDITIONAL INFORMATION Worst Case Current Density 5 2 < A/cm Transistor Count 28,160 Layout Characteristics Step and Repeat 8300µm x 8300µm ISL70002SEH Potential PVIN3 LX3 PGND3 PGND4 LX4 PVIN4 PVIN5 LX5 PGND5 PGND6 LX6 PVIN6 PVIN7 ...
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... PGND10 27 PGND9 28 LX9 29 PVIN9 30 PVIN8 31 LX8 32 PGND8 33 PGND7 34 LX7 35 PVIN7 36 PVIN6 37 LX6 38 PGND6 39 20 ISL70002SEH TABLE 2. LAYOUT X-Y COORDINATES X Y µm) µ 275 7497 275 7117 275 6737 275 6357 275 5977 275 5597 275 5217 335 4672 335 3972 335 3272 ...
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... LX2 50 PGND2 51 PGND1 52 LX1 53 PVIN1 54 SC0 55 SC1 OCSSB 58 OCB 59 OCSSA 60 OCA 61 REF 62 21 ISL70002SEH TABLE 2. LAYOUT X-Y COORDINATES (Continued µm) µ 6115 4784 6967 4996 7853 5226 7853 5595 6967 5825 6115 6037 7853 7855 6967 7625 6115 7413 5723 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 22 ISL70002SEH www.intersil.com/askourstaff http://rel.intersil.com/reports/search.php For additional products, see www ...
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... MIN 0.380 (9.655) 0.370 (9.395) INDEX PASTE 2X0.48 (0.019) REF SEE DETAIL "B" BOTTOM VIEW 23 ISL70002SEH 1.275 (32.39) 1.055 (26.80) 0.567 (14.40) 0.547 (13.90) PIN 1 0.0034 (0.087) MIN TOP VIEW SEE DETAIL “A” 0.100 (2.537) 0.085 (2.157) 0.0075 (0.188) 0.005 (0.125) (0 ...