ISL70002SEH INTERSIL [Intersil Corporation], ISL70002SEH Datasheet - Page 14

• Manufacturer Part Number: ISL70002SEH
• Description: Rad Hard and SEE Hard 12A Synchronous Buck Regulator with Multi-Phase Current Sharing
• Manufacturer: INTERSIL [Intersil Corporation]

Functional Description
The ISL70002SEH is a monolithic, fixed frequency, current-mode
synchronous buck regulator. Two ISL70002SEH devices can be
used to provide a total DC/DC solution for FPGAs, CPLDs, DSPs
and CPUs.
Power Blocks
The power output stage of the regulator consists of ten power
blocks that are paralleled to provide full 12A output current
capability. The block diagram in Figure 12 shows a top level view
of the individual power blocks.
Each power block has a power supply input pin, PVINx, a phase
output pin, LXx, and a power supply ground pin, PGNDx. All PVINx
pins must be connected to a common power supply rail and all
PGNDx pins must be connected to a common ground. LXx pins
should be connected to the output inductor based on the
required load current, but must include the LX2, LX6 and LX9
pins. For example, if 6A of output current is needed, any five LXx
pins can be connected to the inductor as long as three of them
are the LX2, LX6 and LX9 pins. The unused LXx pins should be
left unconnected. Connecting all ten LXx pins to the output
inductor provides a maximum 12A of output current at +150°C
die temperature. See the “Typical Application Schematic” on
page 6 for pin connection guidance.
Power blocks 2, 6 and 9 contain the master pilot devices, which
provides current feedback and this is why they must be
connected to the output inductor.
Main Control Loop
During normal operation, the internal top power switch is turned
on at the beginning of each clock cycle. Current in the output
inductor ramps up until the current comparator trips and turns
off the top power MOSFET. Then the bottom power MOSFET turns
on and the inductor current ramps down for the rest of the cycle.
PGND1
PGND2
PGND3
PGND4
PGND5
PVIN1
PVIN2
PVIN3
PVIN4
PVIN5
LX1
LX2
LX3
LX4
LX5
POWER BLOCK 1
POWER BLOCK 2
POWER BLOCK 4
FIGURE 12. POWER BLOCK DIAGRAM
PWMA and OCPA
POWER BLOCK 3
POWER BLOCK 5
Note: Shaded Blocks indicate pilot current
and overcurrent sensors.
14
POWER BLOCK 10
POWER BLOCK 9
POWER BLOCK 7
POWER BLOCK 8
POWER BLOCK 6
PWMB and OCPB
PWMC
ISL70002SEH
PVIN7
LX7
PVIN10
LX10
PGND10
PVIN9
LX9
PGND9
PGND7
PVIN6
LX6
PGND6
PVIN8
LX8
PGND8
The current comparator compares the output current at the
current ripple peak to the scaled pilot current. The error amplifier
monitors V
voltage. The output voltage of the error amplifier creates a
proportional current to the pilot. If V
the pilot is increased and the trip off current level of the output is
increased. The increased output current raises V
agreement with the reference voltage.
Output Voltage Selection
The output voltage of the ISL70002SEH can be adjusted using an
external resistor divider as shown in Figure 13. R
selected as 1kΩ to mitigate SEE. R
4.7nF ceramic capacitor, C
stability margins. The REF pin should be bypassed to AGND with
a 220nF ceramic capacitor to mitigate SEE. It should be noted
that no current (sourcing or sinking) is available from the REF pin.
R
configure the output voltage from 0.8V to 85% of the input
voltage.
The minimum on time determines the lowest output voltage, so
when VIN = 5.5V and the switching frequency is 500kHz this
parameter limits the regulated output voltage to about 0.8V or
greater. It increases at the 1MHz switching frequency to about
1.6V or greater. The minimum on time increases by about 9% at
V
minimum on time and the 1MHz minimum V
0.9V.
Switching Frequency/Synchronization
The ISL70002SEH features an internal oscillator running at a
fixed frequency of either 500kHz or 1MHz ±15% over
recommended operating conditions. When the FSEL pin is
grounded the oscillator operated at 500kHz, and if FSEL is
connected to DVDD it operates at 1MHZ.
The regulator can be configured to run from the internal oscillator
or can be synchronized to another ISL70002SEH or an SEE
hardened external clock with a frequency range of 500kHz to
1MHz (±20%).
To run the regulator from the internal oscillator, connect the M/S
pin to DVDD. In this case the output of the internal oscillator
R
IN
B
B
can be determined from Equation 3. The designer can
= 3V, but the 500kHz output voltage is not limited by the
=
R
V
C
R
C
T
REF
REF
C
T
⋅
= 1k
= 4.7nF
------------------------------------ -
V
OUT
AMPLIFIER
OUT
FIGURE 13. OUTPUT VOLTAGE SELECTION
= 0.6V
= 220nF
ERROR
V
and compares it with an internal reference
REF
+
-
–
V
V
REF
REF
C
, to mitigate SEE and to improve loop
LXx
FB
REF
L
T
OUT
OUT
should be shunted by a
C
is low, the current level of
REF
C
OUT
OUT
is approximately
OUT
T
R
R
T
should be
V
B
OUT
until it is in
C
April 5, 2012
C
FN8264.1
(EQ. 3)