ATF1508ASVL ATMEL [ATMEL Corporation], ATF1508ASVL Datasheet - Page 12

• Manufacturer Part Number: ATF1508ASVL
• Description: Highperformance EE PLD
• Manufacturer: ATMEL [ATMEL Corporation]

Power-down Mode
The ATF1508ASV(L) includes two pins for optional pin-
controlled power-down feature. When this mode is
enabled, the PD pin acts as the power-down pin. When the
PD1 and PD2 pin is high, the device supply current is
reduced to less than 5 mA. During power-down, all output
data and internal logic states are latched and held. There-
fore, all registered and combinatorial output data remain
valid. Any outputs that were in a high-Z state at the onset
will remain at high-Z. During power-down, all input signals
Power Down AC Characteristics
Notes:
12
Symbol
t
t
t
t
t
t
t
t
t
t
IVDH
GVDH
CVDH
DHIX
DHGX
DHCX
DLIV
DLGV
DLCV
DLOV
1. For slow slew outputs, add t
2. Pin or product term.
Parameter
Valid I, I/O before PD High
Valid OE
Valid Clock
I, I/O Don’t Care after PD High
OE
Clock
PD Low to Valid I, I/O
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
(2)
ATF1508ASV(L)
Don’t Care after PD High
(2)
Don’t Care after PD High
(2)
(2)
before PD High
before PD High
SSO
.
(1)(2)
except the power-down pin are blocked. Input and I/O hold
latches remain active to ensure that pins do not float to
indeterminate levels, further reducing system power. The
power-down pin feature is enabled in the logic design file.
Designs using either power-down pin may not use the PD
pin logic array input. However, buried logic resources in
this macrocell may still be used.
Min
15
15
15
-15
Max
25
25
25
1
1
1
1
Min
20
20
20
-20
Max
30
30
30
1
1
1
1
Units
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs