ATF1508ASVL ATMEL [ATMEL Corporation], ATF1508ASVL Datasheet - Page 6

• Manufacturer Part Number: ATF1508ASVL
• Description: Highperformance EE PLD
• Manufacturer: ATMEL [ATMEL Corporation]

Programmable Pin-keeper Option for
Inputs and I/Os
The ATF1508ASV(L) offers the option of programming all
input and I/O pins so that “pin-keeper” circuits can be uti-
lized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-
level. This circuitry prevents unused input and I/O lines
from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The
keeper circuits eliminate the need for external pull-up resis-
tors and eliminate their DC power consumption.
Input Diagram
Speed/Power Management
The ATF1508ASV(L) has several built-in speed and power
management features. The ATF1508ASV(L) contains cir-
cuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This
not only reduces power consumption during inactive peri-
ods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
To further reduce power, each ATF1508ASV(L) macrocell
has a reduced-power bit feature. This feature allows indi-
vidual macrocells to be configured for maximum power-
savings. This feature may be selected as a design option.
6
ATF1508ASV(L)
I/O Diagram
All ATF1508 also have an optional power-down mode. In
this mode, current drops to below 10 mA. When the power-
down option is selected, either PD1 or PD2 pins (or both)
can be used to power down the part. The power-down
option is selected in the design source file. When enabled,
the device goes into power-down when either PD1 or PD2
is high. In the power-down mode, all internal logic signals
are latched and held, as are any enabled outputs.
All pin transitions are ignored until the PD pin is brought
low. When the power-down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How-
ever, the pin’s macrocell may still be used to generate bur-
ied foldback and cascade logic signals.
All power-down AC characteristic parameters are com-
puted from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder,
t
the data paths t
Each output also has individual slew rate control. This may
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast
switching in the design file.
RPA
, must be added to the AC parameters, which include
LAD
, t
LAC
, t
IC
, t
ACL
, t
ACH
and t
SEXP
.