XC9572XV-4TQ100C XILINX [Xilinx, Inc], XC9572XV-4TQ100C Datasheet

no-image

XC9572XV-4TQ100C

Manufacturer Part Number
XC9572XV-4TQ100C
Description
XC9572XV High-performance CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet
DS052 (v2.2) August 27, 2001
Features
Description
The XC9572XV is a 2.5V CPLD targeted for high-perfor-
mance, low-voltage applications in leading-edge communi-
cations and computing systems. It is comprised of four
54V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 4 ns.
DS052 (v2.2) August 27, 2001
Advance Product Specification
72 macrocells with 1,600 usable gates
Available in small footprint packages
-
-
-
-
Optimized for high-performance 2.5V systems
-
-
Advanced system features
-
-
-
-
-
-
-
-
-
-
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
-
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
44-pin PLCC (34 user I/O pins)
44-pin VQFP (34 user I/O pins)
48-pin CSP (38 user I/O pins)
100-pin TQFP (72-user I/O pins)
Low power operation
Multi-voltage operation
In-system programmable
Two separate output banks
Superior pin-locking and routability with
FastCONNECT II™ switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold ciruitry on all user pin inputs
Full IEEE Standard 1149.1 boundary-scan (JTAG)
Endurance exceeding 10,000 program/erase
cycles
20 year data retention
ESD protection exceeding 2,000V
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
R
0
0
www.xilinx.com
1-800-255-7778
5
XC9572XV High-performance
CPLD
Advance Product Specification
Power Estimation
Power dissipation in CPLDs can vary substantially depend-
ing on the system frequency, design application and output
loading. To help reduce power dissipation, each macrocell
in a XC9500XV device may be configured for low-power
mode (from the default high-performance mode). In addi-
tion, unused product-terms and macrocells are automati-
cally deactivated by the software to further conserve power.
For a general estimate of I
used:
I
Where:
This calculation is based on typical operating conditions
using a pattern of 16-bit up/down counters in each Function
Block with no output loading. The actual I
with the design application and should be verified during
normal system operation.
Figure 1
CC
Figure 1: Typical I
(mA) =
MC
MC
MC
MC = Total number of macrocells used
f = Clock frequency (MHz)
HP
HP
LP
shows the above estimation in a graphical form.
(0.36) + MC
= Macrocells in low-power mode
90
30
70
50
10
= Macrocells in high-performance (default) mode
0
50
LP
CC
Clock Frequency (MHz)
(0.23) + MC(0.005 mA/MHz) f
vs. Frequency for XC9572XV
CC
, the following equation may be
100
150
DS052_01_012501
CC
value varies
200
1

Related parts for XC9572XV-4TQ100C

XC9572XV-4TQ100C Summary of contents

Page 1

... ESD protection exceeding 2,000V Description The XC9572XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 4 ns. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. ...

Page 2

... JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR 2 I/O/GTS Function Block outputs (indicated by the bold line) drive the I/O Blocks directly. 2 JTAG In-System Programming Controller Controller I/O Blocks Figure 2: XC9572XV Architecture www.xilinx.com 1-800-255-7778 54 Function 18 Block 1 Macrocells Function 18 Block 2 Macrocells Function 18 Block 3 Macrocells ...

Page 3

... Program/Erase cycles (endurance Electrostatic Discharge (ESD) ESD DS052 (v2.2) August 27, 2001 Advance Product Specification Description (1) (1) Parameter o Commercial Industrial T = –40 A Parameter www.xilinx.com 1-800-255-7778 XC9572XV High-performance CPLD Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +260 +150 Min Max +70 C 2.37 2. +85 C 2.37 2.62 3.13 3 ...

Page 4

... XC9572XV High-performance CPLD DC Characteristics (Over Recommended Operating Conditions) Symbol Parameter V Output high voltage for 3.3V outputs OH Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs V Output low voltage for 3.3V outputs OL Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs I Input leakage low current ...

Page 5

... DS052 (v2.2) August 27, 2001 Advance Product Specification Output Type V CCIO 3.3V 2. 1.8V Figure 3: AC Load Circuit XC9572XV-4 Min Max - 1.6 - 1.0 - 1.6 - 3 1.4 - 0.6 - 4.0 - 0.2 1.6 - 1.2 - 1 0.2 - 4.7 4.0 - 0.6 - 5.6 - 1.6 - 0.6 - 0.2 - 3.0 Advance Information www.xilinx.com 1-800-255-7778 XC9572XV High-performance CPLD TEST 1 2 3.3V 320 360 2.5V 250 660 1.8V 10K 14K DS051_03_0601000 XC9572XV-5 XC9572XV-7 Min Max Min Max - 2.0 - 2.3 - 1.2 - 1.5 - 2.0 - 3.1 - 4.0 - 5.0 - 2 1.7 - 2.4 - 0.7 - 1.4 - 5.0 - 7 ...

Page 6

... XC9572XV High-performance CPLD XC9572XV I/O Pins Function Macro- Block cell PC44 VQ44 CS48 (1) ( (1) ( (1) ( ...

Page 7

... R XC9572XV Global, JTAG and Power Pins Pin Type PC44 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 2.5V 21, 41 CCINT V 1.8/2.5V/3.3V CCIO GND 10, 23 Connects DS052 (v2.2) August 27, 2001 Advance Product Specification VQ44 ...

Page 8

... Updated I Characteristics and Internal Timing Parameters 08/27/01 2.2 Changed V - added "low" current XC9572XV -7 TQ 100 C Package 44-pin Plastic Lead Chip Carrier (PLCC) 44-pin Very Thin Quad Flat Pack (VQFP) 48-ball Chip Scale Package (CSP) 100-pin Thin Quad Flat Pack (TQFP) 44 Plastic PLCC ...

Related keywords