XC9572XV-7TQ100I XILINX [Xilinx, Inc], XC9572XV-7TQ100I Datasheet

XC9572XV-7TQ100I

Manufacturer Part Number

XC9572XV-7TQ100I

Description

High-performance CPLD

Manufacturer

XILINX [Xilinx, Inc]

Datasheet

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DS052 (v3.0) June 25, 2007

Note: This product is being discontinued. You cannot

order parts after May 14, 2008. Xilinx recommends replac-

ing XC9572XV devices with equivalent XC9572XL devices

in all designs as soon as possible. Recommended replace-

ments are pin compatible, however require a V

3.3V, and a recompile of the design file. In addition, there is

no 1.8V I/O support. See

this

recomendations for the XC9572XV CPLD.

Features

•

Description

The XC9572XV is a 2.5V CPLD targeted for high-perfor-

mance, low-voltage applications in leading-edge communi-

cations and computing systems. It is comprised of four

54V18 Function Blocks, providing 1,600 usable gates with

propagation delays of 5 ns.

Power Estimation

Power dissipation in CPLDs can vary substantially depend-

ing on the system frequency, design application and output

loading. To help reduce power dissipation, each macrocell

DS052 (v3.0) June 25, 2007

Product Specification

72 macrocells with 1,600 usable gates

Available in small footprint packages

Optimized for high-performance 2.5V systems

Advanced system features

Fast concurrent programming

Slew rate control on individual outputs

Enhanced data security features

Excellent quality and reliability

discontinuation,

44-pin VQFP (34 user I/O pins)

100-pin TQFP (72-user I/O pins)

Low power operation

Multi-voltage operation

In-system programmable

Superior pin-locking and routability with

Fast CONNECT™ II switch matrix

Extra wide 54-input Function Blocks

Up to 90 product-terms per macrocell with

individual product-term allocation

Local clock inversion with three global and one

product-term clocks

Individual output enable per output pin

Input hysteresis on all user and boundary-scan pin

inputs

Bus-hold ciruitry on all user pin inputs

Full IEEE Standard 1149.1 boundary-scan (JTAG)

20 year data retention

ESD protection exceeding 2,000V

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

including

XCN07010

device

for details regarding

replacement

change to

www.xilinx.com

XC9572XV High-performance

CPLD

Product Specification

in a XC9500XV device may be configured for low-power

mode (from the default high-performance mode). In addi-

tion, unused product-terms and macrocells are automati-

cally deactivated by the software to further conserve power.

For a general estimate of I

used:

Separating internal and I/O power here is convenient

because XC9500XV CPLDs also separate the correspond-

ing power pins. P

tance driven, so it is handled by I = CVf. I

situation that reflects the actual design considered and the

internal switching speeds. An estimation expression for

where:

This calculation was derived from laboratory measurements

of an XC9500XV part filled with 16-bit counters and allowing

a single output (the LSB) to be enabled. The actual I

value varies with the design application and should be veri-

fied during normal system operation.

above estimation in a graphical form. For a more detailed

discussion of power consumption in this device, see Xilinx

application note

XC9500XV Designs.”

CCINT

frequently a good estimate

MAX

+ 0.171) + 0.04(MC

(mA) = MC

(taken from simulation) is:

TOG

TOTAL

= max clocking frequency in the device

= average p-terms used over low power macrocell

= average p-terms used per high speed macrocell

110

= #macrocells used in low power mode

= # macrocells used in high speed mode

= % macrocells toggling on each clock (12% is

= P

XAPP361, “Planning for High Speed

INT

(0.122 X PT

is a strong function of the load capaci-

+ P

C lock F requency (MH z )

= I

, the following equation may be

+ MC

CCINT

100

+ 0.238) + MC

) x f

x V

Figure 1

150

MAX

CCINT

DS052_01_041405

CCINT

x MC

+ P

shows the

is another

200

TOG

(0.042 x

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XC9572XV-7TQ100I Summary of contents

Page 1

... ESD protection exceeding 2,000V Description The XC9572XV is a 2.5V CPLD targeted for high-perfor- mance, low-voltage applications in leading-edge communi- cations and computing systems comprised of four 54V18 Function Blocks, providing 1,600 usable gates with propagation delays of 5 ns. Power Estimation ...

Page 2

... Figure 1: Typical ICC vs. Frequency for XC9572XV JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O I/O/GCK I/O/GSR I/O/GTS Figure 2: XC9572XV Architecture (Function Block outputs (indicated by the bold line) drive the I/O Blocks directly) Supported I/O Standards Table 1: IOSTANDARD Options IOSTANDARD V CCIO LVTTL 3.3V LVCMOS2 2.5V X25TO18 1.8V The XC9572XV CPLD features both LVCMOS and LVTTL I/O implementations ...

Page 3

... DR N Program/Erase cycles (endurance Electrostatic Discharge (ESD) ESD DS052 (v3.0) June 25, 2007 Product Specification Description (1) (1) . Parameter o Commercial Industrial T = –40 A Parameter www.xilinx.com XC9572XV High-performance CPLD Value –0.5 to 2.7 –0.5 to 3.6 –0.5 to 3.6 –0.5 to 3.6 –65 to +150 +150 Min Max +70 C 2.37 2. +85 C 2.37 2.62 3.0 3.6 2.37 2.62 1 ...

Page 4

... XC9572XV High-performance CPLD DC Characteristics (Over Recommended Operating Conditions) Symbol Parameter V Output high voltage for 3.3V outputs OH Output high voltage for 2.5V outputs Output high voltage for 1.8V outputs V Output low voltage for 3.3V outputs OL Output low voltage for 2.5V outputs Output low voltage for 1.8V outputs I Input leakage current ...

Page 5

... Adjacent macrocell p-term allocator delay PTA2 T Slew-rate limited delay SLEW DS052 (v3.0) June 25, 2007 Product Specification Output Type V CCIO 3.3V 2. 1.8V Figure 3: AC Load Circuit Parameter www.xilinx.com XC9572XV High-performance CPLD TEST 1 2 3.3V 320Ω 360Ω 2.5V 250Ω 660Ω 1.8V 10KΩ 14KΩ XC9572XV-5 XC9572XV-7 ...

Page 6

... XC9572XV High-performance CPLD XC9572XV I/O Pins Function Macro- Block cell VQ44 ( ( ( ...

Page 7

... R XC9572XV Global, JTAG and Power Pins Pin Type VQ44 I/O/GCK1 I/O/GCK2 I/O/GCK3 I/O/GTS1 I/O/GTS2 I/O/GSR TCK TDI TDO TMS V 2.5V 15, 35 CCINT V 1.8/2.5V/3.3V CCIO GND 4, 17 Connects DS052 (v3.0) June 25, 2007 Product Specification TQ100 ...

Page 8

... Speed Device Ordering and (pin-to-pin Part Marking Number delay) XC9572XV-5VQ44C 5 ns XC9572XV-5TQ100C 5 ns XC9572XV-7VQ44C 7.5 ns XC9572XV-7TQ100C 7.5 ns XC9572XV-7VQ44I 7.5 ns XC9572XV-7TQ100I 7.5 ns Notes Commercial 0° to +70° Industrial Some packages available in Pb-free option. See 8 R XC95xxxXV TQ144 7C 1 Sample package with part marking. ...

Page 9

... DC characteristics: I CCIO - changed to "Input leakage high current"; Internal Timing from 6.5 to 5.9. AOI equation on page 1. Updated Component Availability Chart. Changed from 260 to 220 C. Updated Device Part Marking. SOL specification to AC Characteristics. Added IOSTANDARD information. APRPW www.xilinx.com XC9572XV High-performance CPLD Description ...

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