ADSP-1981BL AD [Analog Devices], ADSP-1981BL Datasheet
ADSP-1981BL
Related parts for ADSP-1981BL
ADSP-1981BL Summary of contents
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AC ’97 2.3 COMPATIBLE FEATURES S/PDIF output, 20-bit data format, supporting 48 kHz and 44.1 kHz sample rates Integrated stereo headphone amplifier Variable sample rate audio External audio power-down control >90 dB dynamic range Stereo full-duplex codec 20-bit PCM DAC ...
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AD1981BL TABLE OF CONTENTS Specifications..................................................................................... 3 Test Conditions............................................................................. 3 General Specifications ................................................................. 3 Power-Down States ...................................................................... 5 Timing Parameters ....................................................................... 5 Absolute Maximum Ratings............................................................ 9 Environmental Conditions.......................................................... 9 Pin Configuration and Function Descriptions........................... 10 Indexed Control Registers ............................................................. 12 Control ...
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SPECIFICATIONS TEST CONDITIONS Standard test conditions, unless otherwise noted. Table 1. Parameter Temperature Digital Supply ( Analog Supply ( Sample Rate ( Input Signal Analog Output Pass Band DAC ADC GENERAL SPECIFICATIONS Table 2. ...
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AD1981BL Parameter Step Size (+ −34.5 dB) (All Steps Tested): MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC Input Gain/Attenuation Range: MIC_IN, LINE_IN, CD, AUX, PHONE_IN, DAC DIGITAL DECIMATION AND INTERPOLATION FILTERS Pass Band Pass-Band Ripple Transition Band Stop Band ...
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Parameter Low Level Output Voltage ( Input Leakage Current Output Leakage Current POWER SUPPLY Power Supply Range (AV and Power Dissipation Analog Supply Current—3.3 V (AV DD Digital Supply Current—3.3 ...
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AD1981BL Parameter SYNC Period Setup to Falling Edge of BIT_CLK Hold from Falling Edge of BIT_CLK BIT_CLK Rise Time BIT_CLK Fall Time SYNC Rise Time SYNC Fall Time SDATA_IN Rise Time SDATA_IN Fall Time SDATA_OUT Rise Time SDATA_OUT Fall Time ...
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CLK_LOW BIT_CLK t CLK_HIGH t CLK_PERIOD t SYNC_LOW SYNC t SYNC_HIGH t SYNC_PERIOD Figure 4. Clock Timing BIT_CLK t RISECLK SYNC t RISESYNC SDATA_IN t RISEDIN SDATA_OUT t RISEDOUT Figure 5. Signal Rise and Fall Times SLOT 1 SLOT ...
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AD1981BL BIT_CLK SDATA_OUT SDATA_IN SETUP SYNC t HOLD Figure 7. AC-Link Low Power Mode Timing, SYNC and BIT_CLK Chopped RESET SDATA_OUT t SETUP2RST SDATA_IN, BIT_CLK, EAPD, SPDIF_OUT AND DIGITAL ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 5. Parameter Rating Power Supplies Digital (DV ) −0 +3 Analog (AV ) −0 +6 Input Current (Except Supply Pins) ±10 ...
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AD1981BL PIN CONFIGURATION AND FUNCTION DESCRIPTIONS XTL_OUT SDATA_OUT BIT_CLK SDATA_IN Table 7. Pin Function Descriptions Pin No. Mnemonic DIGITAL I/O 2 XTL_IN 3 XTL_OUT 5 SDATA_OUT 6 BIT_CLK 8 SDATA_IN 10 SYNC 11 RESET 48 SPDIF 1 CHIP SELECTS 45 ...
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Pin No. Mnemonic 22 MIC2 23 LINE_IN_L 24 LINE_IN_R 35 LINE_OUT_L 36 LINE_OUT_R 37 MONO_OUT 39 HP_OUT_L 41 HP_OUT_R 2 FILTER/REFERENCE 27 V REF 28 V REFOUT 29 AFILT1 30 AFILT2 31 AFILT3 32 AFILT4 POWER AND GROUND SIGNALS 1 ...
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AD1981BL INDEXED CONTROL REGISTERS Table 8. Reg Name D15 D14 D13 0x00 Reset X SE4 SE3 0x02 Master Volume 0x04 Headphone HPM X X Volume 0x06 Mono MVM X X Volume 0x0C Phone PHM X X Volume ...
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CONTROL REGISTER DETAILS RESET REGISTER Index 0x00 Reg No. Name D15 D14 D13 0x00 Reset X SE4 SE3 wild card, and has no effect on the value. Writing any value to this register performs a register reset ...
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AD1981BL HEADPHONE VOLUME REGISTER Index 0x04 This register controls the headphone volume controls for both stereo channels and the mute bit. Each volume subregister contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ...
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MONO VOLUME REGISTER Index 0x06 This register controls the mono output volume and mute bit. The volume register contains five bits, generating 32 volume levels with 31 steps of 1.5 dB each. Because AC ’97 defines 6-bit volume registers, to ...
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AD1981BL MIC VOLUME REGISTER Index 0x0E Reg No. Name D15 D14 D13 0x0E MIC Volume MCM X X All registers are not shown, and bits containing an X are assumed to be reserved. Refer to Table 17 for examples. Table ...
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CD VOLUME REGISTER Index 0x12 Reg No. Name D15 D14 D13 0x12 CD Volume CVM For AC ‘97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables separate ...
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AD1981BL PCM-OUT VOLUME REGISTER Index 0x18 Reg No. Name D15 D14 D13 0x18 PCM-Out Volume 1 For AC ’97 compatibility, Bit D7 (RM) is available only by setting the MSPLT bit, Register 0x76. The MSPLT bit enables ...
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RECORD SELECT CONTROL REGISTER Index 0x1A Reg No. Name D15 D14 0x1A Record Select X X Used to select the record source independently for right and left. The default value is 0x0000, which corresponds to MIC In. Refer to Table ...
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AD1981BL Table 26. Settings for Record Gain Register Reg. 0x76 Left-Channel Input Mixer D [11:8] 1 MSPLT D15 Write 0 0 1111 0 0 0000 0 1 XXXX 1 0 1111 1 1 XXXX 1 1 XXXX 1 For AC ...
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POWER-DOWN CONTROL/STATUS REGISTER Index 0x26 Reg No. Name D15 D14 0x26 Power-Down Ctrl/Stat EAPD PR6 The ready bits are read-only; writing to REF, ANL, DAC, ADC has no effect. These bits indicate the status for the AD1981BL subsections. If the ...
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AD1981BL EXTENDED AUDIO ID REGISTER Index 0x28 Reg No. Name D15 D14 D13 0x28 Ext’d Audio ID IDC1 IDC0 X The extended audio ID register identifies which extended audio features are supported. A nonzero extended audio ID value indicates that ...
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Bit Mnemonic SPCV SPDIF Configuration Valid (Read-Only) VFORCE Validity Force Bit (Reset Default = 0) Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments Codec ID Function 00 2-Channel Primary w/SPDIF 00 4-Channel Primary w/SPDIF 00 6-Channel Primary w/SPDIF ...
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AD1981BL SPDIF CONTROL REGISTER Index 0x3A Reg No. Name D15 D14 D13 0x3A SPDIF Control V X SPSR1 Register 0x3A is a read/write register that controls SPDIF functionality and manages bit fields propagated as channel status (or subframe in the ...
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Bit Mnemonic CHS Channel Select SYM Symmetry MAD Mixer ADC Loopback LBEN Enable EQM Equalizer Mute Function biquad 1 coef a2 BCA[5:0] = 011110 biquad 1 coef b1 BCA[5:0] = 100010 biquad 1 coef b2 BCA[5:0] = 100001 biquad 2 ...
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AD1981BL EQ DATA REGISTER Index 0x62 Reg No. Name D15 D14 D13 D12 0x62 EQ CFD15 CFD14 CFD13 CFD12 Data This read/write register is used to transfer EQ biquad coefficients into memory. The register data is transferred to, or retrieved ...
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JACK SENSE/AUDIO INTERRUPT/STATUS REGISTER Index 0x72 Reg No. Name D15 D14 D13 D12 0x72 Jack Sense MT2 All register bits are read/write except for JS0ST and JS1ST, which are read-only. All registers are not shown, and ...
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AD1981BL Table 41. Jack Sense Mute Select—JSMT [2:0] JS1 JS0 Ref Headphone LINE_OUT JSMT2 0 OUT (0) OUT ( OUT ( (1) OUT ( ( OUT ...
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SERIAL CONFIGURATION REGISTER Index 0x74 Reg No. Name D15 D14 D13 0x74 Serial SLOT16 REGM2 REGM1 Config This register is not reset when the reset register (Register 0x00) is written. All registers are not shown, and bits containing an X ...
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AD1981BL Bit Mnemonic VREFD V Disable REFOUT VREFH V High REFOUT MADST Mixer ADC Status Bit 2CMIC 2-Channel MIC Select MADPD Mixer ADC Power-Down FMXE Front DAC into Mixer Enable DAM Digital Audio Mode LODIS LINE_OUT Disable MSPLT Mute Split ...
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VENDOR ID REGISTERS Index 0x7C–0x7E Reg No. Name D15 D14 0x7C Vendor ID1 F7 F6 S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D. Reg No. Name D15 D14 D13 0x7E Vendor ID2 ...
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AD1981BL OUTLINE DIMENSIONS 1.45 1.40 1.35 0.15 0.05 VIEW A ROTATED 90° CCW ORDERING GUIDE Model Temperature Range AD1981BLJST 0°C to 70°C AD1981BLJST-REEL 0°C to 70°C 1 AD1981BLJSTZ 0°C to 70°C 1 AD1981BLJSTZ-REEL 0°C to 70° Pb-free ...