ADSP-1981BL AD [Analog Devices], ADSP-1981BL Datasheet - Page 23

• Manufacturer Part Number: ADSP-1981BL
• Description: AC 97 SoundMAX Codec
• Manufacturer: AD [Analog Devices]

Bit
SPCV
VFORCE
Table 32. AC ’97 2.2 AMAP-Compliant Default SPDIF Slot Assignments
Codec ID
00
00
00
01
01
10
10
11
PCM FRONT DAC RATE REGISTER
Index 0x2C
Reg
No.
0x2C
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 33.
Bit
SRF [15:0]
PCM ADC RATE REGISTER
Index 0x32
Reg
No.
0x32
This read/write sample rate control register contains a 16-bit unsigned value, representing the rate of operation in Hz.
Table 34.
Bit
SRA [15:0]
Name
PCM
Front
DAC
Rate
Name
PCM L/R
ADC
Rate
Mnemonic
SPDIF Configuration Valid
(Read-Only)
Validity Force Bit
(Reset Default = 0)
Mnemonic
Sample Rate
Mnemonic
Sample Rate
Function
2-Channel Primary w/SPDIF
4-Channel Primary w/SPDIF
6-Channel Primary w/SPDIF
+2-Channel Secondary w/SPDIF
+4-Channel Secondary w/SPDIF
+2-Channel Secondary w/SPDIF
+4-Channel Secondary w/SPDIF
+2-Channel Secondary w/SPDIF
D15
SRF15
D15
SRA15
D14
SRF14
D14
SRA14
Function
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
D13
SRF13
Function
The sampling frequency range is from 7 kHz (0x1B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to
VRA, the sample rate is reset to 48 kHz.
D13
SRA13
D12
SRF12
D12
SRA12
Function
This bit indicates the status of the SPDIF transmitter subsystem, enabling the driver to
determine if the currently programmed SPDIF configuration is supported. SPCV is always valid,
independent of the SPDIF enable bit status.
SPCV = 0 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is not
valid (not supported).
SPCV = 1 indicates that the current SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS) is valid
(supported).
When asserted, this bit forces the SPDIF stream validity flag (Bit 28 within each SPDIF L/R
subframe) to be controlled by the V bit (D15) in Register 0x3A (SPDIF control register).
VFORCE = 0 and V = 0; the validity bit is managed by the codec error detection logic.
VFORCE = 0 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
VFORCE = 1 and V = 0; the validity bit is forced low, indicating the subframe data is valid.
VFORCE = 1 and V = 1; the validity bit is forced high, indicating the subframe data is invalid.
D11
SRF11
D11
SRA11
SPSA = 00
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
3 and 4
D10
SRF10
D10
SRA10
Rev. A | Page 23 of 32
D9
SRF9
D9
SRA9
SPSA = 01
7 and 8 (default)
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
7 and 8
D8
SRF8
D8
SRA8
D7
SRF7
D7
SRA7
D6
SRF6
D6
SRA6
D5
SRF5
SPSA = 10
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9 (default)
6 and 9
6 and 9
D5
SRA5
D4
SRF4
D4
SRA4
D3
SRF3
D3
SRA3
D2
SRF2
D2
SRA2
SPSA = 11
10 and 11
10 and 11
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
10 and 11 (default)
D1
SRF1
D1
SRA1
AD1981BL
D0
SRF0
D0
SRA0
Default
0xBB80
Default
0xBB80