ADSP-BF561_06 AD [Analog Devices], ADSP-BF561_06 Datasheet - Page 28

• Manufacturer Part Number: ADSP-BF561_06
• Description: Blackfin Embedded Symmetric Multiprocessor
• Manufacturer: AD [Analog Devices]

ADSP-BF561
Parallel Peripheral Interface Timing
Table
Peripheral Interface operations.
Table 21. Parallel Peripheral Interface Timing
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
For PPI modes that use an internally generated frame sync, the PPI_CLK frequency cannot exceed f
PCLKW
PCLK
SFSPE
HFSPE
SDRPE
HDRPE
DFSPE
HOFSPE
DDTPE
HDTPE
cannot exceed 75MHz and f
POLC = 0
PPI_CLK
PPI_CLK
POLC = 1
PPI_FS1
PPI_FS2
PPI_DATA
21, and
POLS = 1
POLS = 0
POLS = 1
POLS = 0
PPI_CLK Width
PPI_CLK Period
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
Receive Data Setup Before PPI_CLK
Receive Data Hold After PPI_CLK
Internal Frame Sync Delay After PPI_CLK
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
Transmit Data Hold After PPI_CLK
Figure 13
through
SCLK
1
should be equal to or greater than PPI_CLK.
1
Figure 16
, describe Parallel
Figure 13. PPI GP Rx Mode with Internal Frame Sync Timing
t
HOFSPE
FRAME
SYNC IS
DRIVEN
OUT
Rev. A | Page 28 of 60 | May 2006
t
DFSPE
t
SDRPE
DATA0
IS
SAMPLED
t
HDRPE
SCLK
/2. For modes with no frame syncs or external frame syncs, PPI_CLK
Min
5.0
13.3
4.0
1.0
3.5
2.0
1.7
2.0
Max
8.0
8.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns