Z8932120FSC ZILOG [Zilog, Inc.], Z8932120FSC Datasheet - Page 22

• Manufacturer Part Number: Z8932120FSC
• Description: 16-BIT DIGITAL SIGNAL PROCESSORS
• Manufacturer: ZILOG [Zilog, Inc.]

Z89321/371/391
16-Bit Digital Signal Processors
The status register can always be read in its entirety. S15-
S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be writ-
ten by software (Table 6).
22
S2
S15 S14 S13
0
0
0
0
1
1
1
1
N
* The output value is the opposite of the status register content.
OV
Table 6. RPL Description
Z
S1
0
0
1
1
0
0
1
1
S12
C
S11
UI1
UI0 SH3
S10
S0
0
1
0
1
0
1
0
1
S9
OP
S8
Loop Size
Figure 18. Status Register
S7
IE
256
128
P R E L I M I N A R Y
16
32
64
2
4
8
UO1 UO0
S6
S5
S15-S12 are set/reset by the ALU after an operation. S11-
S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift op-
tion is used, then the shifter shifts the result three bits right.
This feature allows the data to be scaled and prevents
overflows.
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
External Register, EXT4-EXT7, are used by the CODEC
interface and 13-bit timer, the registers are reviewed in the
CODEC interface section.
S4
S3
S2
RPL
S1
S0
MPY output arithmetically shifted
right by three bits
Overflow protection
Overflow
Negative
Ram Pointer Loop Size
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
"Short Form Direct" bits
User Output 0-1*
Interrupt Enable
User Input 0-1 (Read Only)
Carry
Zero
256
2
4
8
16
32
64
128
DS97DSP0100
Zilog