Z8932320AEC ZILOG [Zilog, Inc.], Z8932320AEC Datasheet
Z8932320AEC
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Z8932320AEC Summary of contents
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FEATURES Device Package Z89223 44-PLCC, 44-PQFP Z89273 44-PLCC Z89323 64-TQFP, 68-PLCC, 80-PQFP Z89373 64-TQFP, 68-PLCC, 80-PQFP Operating Range 5V ±10% • 0°C to 70°C Standard Temperature • –40°C to +85°C Extended Temperature DSP Core 16-Bit Fixed Point DSP, 24-Bit ALU ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter GENERAL DESCRIPTION (Continued) OTP version of the Z89223/323, is ideal for prototypes and early production builds. Throughout this specification, references to the Z893x3 de- vice apply equally to the Z89223/273/323/373, unless oth- ...
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ZiLOG External Bus and External Registers. made to clarify naming conventions used in this specifica- tion. The external bus and external registers are external to Z893x3 External Register Internal Peripheral DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter The following ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN FUNCTIONS External Address Bus (output, latched). These EA2–EA0. pins provide the External Register Address. This address bus is driven during both internal and external accesses. One seven user-defined ...
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ZiLOG Counter/Timer Output or User Output 1 (out- TMO1/UO1. put). Counter/Timer 0 and Counter/Timer 1 can be pro- grammed to provide output on this pin. When User Outputs are enabled, and the Counter/Timer is disabled, this pin pro- vides the ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS ED3/P0.3 ED4/P0 ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0 ED10/P0.10 ED11/P0.11 Figure 3. 44-Pin PLCC Z89223/273 Pin Configuration ...
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ZiLOG Table 1. 44-Pin PLCC Z89223/273 Pin Description No Symbol Function 1 P2.0/INT0 Port 2.0/Interrupt 0 2 ED12/P0.12 External Data Bus/Port0 3 ED13/P0.13 External Data Bus/Port0 4 ED14/P0.14 External Data Bus/Port0 5 V Ground SS 6 ED15/P0.15 External Data Bus/Port0 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued) ED3/P0.3 ED4/P0.4 ED5/P0.5 ED6/P0.6 ED7/P0.7 ED8/P0.8 ED9/P0.9 ED10/P0.10 ED11/P0.11 Figure 4. 44-Pin PQFP Z89223/273 Pin Configuration ...
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ZiLOG Table 2. 44-Pin PQFP Z89223/273 Pin Description No Symbol Function 1 ED3/P0.3 External Data Bus/Port0 2 ED4/P0.4 External Data Bus/Port0 3 V Ground SS 4 ED5/P0.5 External Data Bus/Port0 5 ED6/P0.6 External Data Bus/Port0 6 ED7/P0.7 External Data Bus/Port0 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 V SS P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 ED13/P0. ED14/P0. ED15/P0.15 Figure 5. 64-Pin TQFP Z89323/373 Pin Configuration 10 ...
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ZiLOG Table 3. 64-Pin TQFP Z89223/273 Pin Description No Symbol Function 1 ED3/P0.3 External Data Bus/Port0 2 ED4/P0.4 External Data Bus/Port0 3 V Ground Power Supply DD 5 ED5/P0.5 External Data Bus/Port0 6 P1.3/SDO Port 1.3/Serial Output ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued) NC ED3/P0.3 ED4/P0 ED5/P0.5 P1.3/SDO ED6/P0.6 P1.4/SS ED7/P0.7 P1.5/SCLK P2.7 ED8/P0.8 ED9/P0 ED10/P0. Figure 6. 68-Pin PLCC Z89323/373 Pin Configuration 12 ...
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ZiLOG Table 4. 68-Pin PLCC Z89323/373 Pin Description No Symbol Function 1 P1.2/SDI Port 1.2/Serial Input 2 P2.0/INT0 Port 2.0/Interrupt 0 3 ED12/P0.12 External Data Bus/Port0 4 ED13/P0.13 External Data Bus/Port0 Power Supply ED14/P0.14 External Data ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PIN CONFIGURATIONS (Continued P30 ED0/P0.0 ED1/P0.1 ED2/P0.2 P1.0/INT2 P1.1/CLKOUT P1.2/SDI P2.0/INT0 ED12/P0.12 75 ED13/P0. ED14/P0. P3 Figure 7. 80-Pin ...
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ZiLOG Table 5. 80-Pin PQFP Z89323/373 Pin Description No Symbol Function Connection 2 ED15/P0.15 External Data Bus/Port0 Connection Connection 5 ED3/P0.3 External Data Bus/Port0 6 P3.2 Port 3.2 7 ED4/P0.4 External ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ABSOLUTE MAXIMUM RATINGS Symbol Description V Supply Voltage CC T Storage Temperature –65 STG T Ambient Operating A Temperature “S” device “E” device STANDARD TEST CONDITIONS The characteristics listed below apply for ...
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ZiLOG DC ELECTRICAL CHARACTERISTICS Table 6. ROM Version –40°C to +85°C for “E” temperature range, unless otherwise noted; A Symbol Parameter I Supply Current using PLL DD–PLL I Supply Current using External Clock Direct DD–ECD I Supply ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter DC ELECTRICAL CHARACTERISTICS (Continued Direct Clock with VCO Off PLL Clock from 32.8KHz Crystal Figure 9. Z89373 Typical OTP Current Consumption 18 10 ...
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ZiLOG AC ELECTRICAL CHARACTERISTICS Table –40°C to +85°C for “E” temperature range, unless otherwise noted A Symbol Parameter Clock TCY CLKI Cycle Time for user-supplied clock CPWH CLKI Pulse Width High CPWL CLKI Pulse Width ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter 8-BIT ANALOG/DIGITAL CONVERTER T = 0°C to +70°C for “S” temperature range, unless otherwise noted A Parameter Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Zero Offset Error Full Scale Offset Error Valid Input ...
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ZiLOG TIMING DIAGRAMS RD/WR DS EA(2:0) ED(15:0) RD/WR DS WLAT WAIT CLKOUT EA(2:0) ED(15:0) DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter TCY CPWL Figure 10. Clock Timing RWSET EASET Valid Address Out RDSET Data Figure 11. Read Timing WDEA ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter TIMING DIAGRAMS (Continued) RD/WR DS EA(2:0) ED(15:0) RD/WR RWSET DS WLAT WAIT CLKOUT EASET EA(2:0) WRVALID ED(15:0) 22 RWSET EASET Valid Address Out WRVALID Data Figure 13. Write Timing WDEA Valid Address ...
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ZiLOG SS* SS-SDO Valid SCLK* SCLK-SDO Valid SDO TRI-STATE SDI *Notes: The polarity of SCLK and SS are programmable by the user used in Slave Mode only. This figure illustrates data transmission on the falling edge of SCLK, ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter FUNCTIONAL DESCRIPTION Most instructions are executed in one Instruction Timing. machine cycle. A multiplication or multiply/accumulate in- struction requires a single cycle. Long immediate instruc- tions, and Jump or Call instructions, are ...
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ZiLOG The Z893x3 features three user interrupt inputs Interrupts. which can be programmed to be positive or negative edge- triggered. There are five interrupts generated by internal pe- ripherals: the A/D converter, the Serial Peripheral Interface, and the three Counter/Timers. ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter MEMORY MAP Programs words can be Program Memory. masked into internal ROM (Z89323) or programmed into OTP (Z89373). Four locations are dedicated to the vector addresses for the ...
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ZiLOG REGISTERS Both external and internal registers are accessed in one ma- chine cycle. The external registers are used to access the on- chip peripherals when they are enabled. The internal registers of the Z893X3 are defined below: Register Register ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter REGISTERS (Continued) Table 12. RPL Description The following are not actually registers, but are ...
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ZiLOG BANK/EXT REGISTER ASSIGNMENTS There are 16 different Banks of EXT registers. Control of the bank switching is done via the EXT7 register. The same EXT7 register exists in all Banks. Banks 0–5 support different combinations of external reg- isters ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter BANK/EXT REGISTER ASSIGNMENTS (Continued) Interrupt Status/Bank Select RegisterÑEXT7 Following is a description of EXT7. It contains both a Bank Select Field and Interrupt Status Bits. Bank Select Field. The four LSBs of ...
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ZiLOG Interrupt Allocation Register Bits 3–0 of the Interrupt Allocation Register define which unique interrupt source the highest priority, and is allocated to ISR0 (Interrupt Service Request 0). Bits 7–4 of the Interrupt Allocation Register define which unique interrupt source ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter BANK/EXT REGISTER ASSIGNMENTS (Continued) Interrupt Polarity Register Ñ The trigger polarities, rising-edge or falling-edge, of all the external interrupts are programmable. Bank 14/Ext 6 Reg D15 D14 D13 D12 D11 D10 D9 ...
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ZiLOG I/O PORTS I/O pin allocation of ports for the different package types is designed to provide configuration flexibility. Each port line of Ports 0, 1, and 2 can be independently selected as 44-Pin PLCC, Device Pins 44-Pin PQFP P0 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter I/O PORTS (Continued) Port0Ñ16-Bit Programmable I/O Bank15/EXT0 is the Port0 direction control register. Bank15/EXT1 includes specific bits to enable and config- ure Port0. The Port0 data register is Ext4 in Banks 0, ...
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ZiLOG Port1Ñ8-Bit Programmable I/O Bank15/EXT1 is the Port1 control register. The MSB is the Port1 direction control. Port1 data is accessed as the LSB of EXT5 in Banks The Port1 pins can also be mapped to ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter I/O PORTS (Continued) Port2Ñ8-Bit Programmable I/O Bank15/EXT2 is the Port2 control register. The LSB is the Port2 direction control. Port2 data is accessed as the MSB of EXT5 in Banks 0,1,or 5. ...
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ZiLOG Port3Ñ8-BIt Programmable I/O Port3 is an additional I/O port available only in the 80-pin package. P3.3–P3.0 are inputs and P3.7–P3.4 are outputs. Bit 8 of Bank15/EXT2 enables and disables Port3. The LSB of Bank2/EXT5 is the Port3 Data Register. ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PERIPHERALS Analog to Digital Converter (A/D) The A 4-channel 8-bit half-flash converter. It uses two reference resistor ladders, one for the upper 5 bits, and another for the lower 3 ...
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ZiLOG Bank13/EXT0 (LSB CSEL0 CSEL1 (Reserved) SCAN QUAD DIV0 DIV1 DIV2 Figure 29. ADCTL Register (LSB) Table 18. A/D Prescaler Values (Bits DIV2 DIV1 DIV0 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PERIPHERALS (Continued) Counter/Timers (C/T0 and C/T1) The Z893x3 features two 16-bit Counter/Timers (C/T) that can be independently configured to operate in various modes. Each is implemented as a 16-bit Load Register and ...
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ZiLOG Bank 13/EXT1 (C/T0) and Bank14/EXT1 (C/T1) D15 D14 D13 D12 D11 D10 D9 D8 *Note: The user should always program this bit to "0". C/T Registers Each C/T contains a set of five 16-bit Registers. Bank13 is used to ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PERIPHERALS (Continued) TPR—Prescaler Register (Bank13,14/EXT5). 8-bit down counter that holds the current Prescaler Count Value. It can be read like any other ordinary register. How- ever, writing to TPR is different than ...
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ZiLOG GENERAL-PURPOSE COUNTER/TIMER (C/T2) This versatile16-bit C/T offers multiple uses, including Sleep Mode Wake-up. It can be clocked with the slow 32 kHz crystal clock (CLKI), while the DSP and other pe- ripheral functions operate at a higher frequency generated ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter GENERAL-PURPOSE COUNTER/TIMER (C/T2) (Continued) Bank 15/EXT2 D15 D14 D13 D12 D11 D10 Figure 38. Counter/Timer2 Control Register Port2 I/O Directions 0 ...
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ZiLOG SERIAL PERIPHERAL INTERFACE The Z893x3 incorporates a Serial Peripheral Interface (SPI) for communication with other microcontrollers and periph- erals. The SPI can be operated either as the system Master system Slave. The SPI consists of three ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter SERIAL PERIPHERAL INTERFACE (Continued) Slave Mode Operation SS must be asserted to enable a data transfer. Incoming data on the SDI pin is shifted into the SPI Shift Register one data bit ...
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ZiLOG SYSTEM CLOCK GENERATOR The System Clock can be generated from an external clock signal, or from the internal crystal oscillator. For the latter case, a 32-kHz crystal is used in conjunction with the in- ternal crystal oscillator. The system ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter SYSTEM CLOCK GENERATOR (Continued) mined by the PLL Divisor value in the MSB of the Clock Control Register, Bank15/EXT5: VCO Frequency = 4 x PLL Divisor x PLL In Frequency. The PLL ...
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ZiLOG INSTRUCTION SET The addressing modes are: <pregs>, <hwregs>. These modes are used for loads to and from registers within the chip, such as loading to the accumulator, or loading from a pointer register. The names of the registers are ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter CONDITION CODES The following Instruction Description defines the condition codes supported by the DSP assembler. If the instruction description refers to the <cc> (condition code) symbol in one of its addressing modes, ...
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ZiLOG INSTRUCTION DESCRIPTIONS Inst. Description Synopsis ABS Absolute ABS[<cc>,]<src> Value ADD Addition ADD<dest>,<src> AND Bitwise AND AND<dest>,<src> CALL Subroutine CALL call [<cc>,]<address> CCF Clear C flag CCF CIEF Clear IE Flag CIEF COPF Clear OP flag COPF CP Comparison CP<src1>,<src2> ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis LD Load LD<dest>,<src> destination with source Notes: When <dest> is <hwregs>, <dest> cannot be P. When <dest> is <hwregs> and <src> is <hwregs>, <dest> cannot be ...
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ZiLOG Inst. Description Synopsis Notes: If src1 is <regind> it must be a bank 1 register. Src2’s <regind> must be a bank 0 register. <hwregs> for src1 cannot be X. For the operands <hwregs>, <regind> the <bank switch> defaults to ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter INSTRUCTION DESCRIPTIONS (Continued) Inst. Description Synopsis XOR Bitwise XOR <dest>,<src> exclusive OR The third (optional) operand of Bank Switch Operand. the MLD, MPYA and MPYS instructions represents wheth- er the bank switch ...
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ZiLOG PACKAGE INFORMATION DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter Figure 44. 44-Pin PLCC Package Diagram Figure 45. 44-Pin PQFP Package Diagram Z89223/273/323/373 55 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PACKAGE INFORMATION (Continued) 56 Figure 46. 64-Pin TQFP Package Diagram ZiLOG DS000202-DSP0599 ...
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ZiLOG DS000202-DSP0599 16-Bit Digital Signal Processors with A/D Converter Figure 47. 68-Pin PLCC Package Diagram Z89223/273/323/373 57 ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter PACKAGE INFORMATION (Continued) 58 Figure 48. 80-Pin PQFP Package Diagram ZiLOG DS000202-DSP0599 ...
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... ORDERING INFORMATION Package Type ROM 44-Pin PLCC Z8922320VSC Z8922320VEC 44-Pin PQFP Z8922320FSC Z8922320FEC 64-Pin TQFP Z8932320ASC Z8932320AEC 68-Pin PLCC Z8932320VSC Z8932320VEC 80-Pin PQFP Z8932320FSC Z8932320FEC For fast results, contact your local ZiLOG sales office for assistance in ordering the part required. CODES Package ...
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Z89223/273/323/373 16-Bit Digital Signal Processors with A/D Converter ©1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ...