Z8932320AEC ZILOG [Zilog, Inc.], Z8932320AEC Datasheet - Page 32

• Manufacturer Part Number: Z8932320AEC
• Description: 16-BIT DIGITAL SIGNAL PROCESSORS WITH A/D CONVERTER
• Manufacturer: ZILOG [Zilog, Inc.]

BANK/EXT REGISTER ASSIGNMENTS (Continued)
Z89223/273/323/373
16-Bit Digital Signal Processors with A/D Converter
Interrupt Polarity Register
The trigger polarities, rising-edge or falling-edge, of all the
external interrupts are programmable.
Wait-State Control RegisterÑBank15/EXT3
The Wait-State Control Register enables the insertion of
wait states when the DSP accesses slow peripherals. This
register enables the insertion of one wait state on the ED
bus, providing 100 ns of access time instead of 50 ns when
operating at 20 MHz. When more than one wait state is nec-
32
Bank15/EXT3 Reg
D15 D14 D13 D12 D11 D10 D9
Bank 14/Ext 6 Reg
D15 D14 D13 D12 D11 D10 D9 D8
Ñ
Bank14/EXT6
D8
Figure 23. Wait-State Control Register
D7
Figure 22. Interrupt Polarity Register
D6
D5
D7 D6
D4
D5 D4 D3 D2
D3
D2
essary, input pin P2.4/ WAIT can be used to provide addi-
tional wait states. The Wait-State Register enables the user
to specify which EXT registers, EXT0–EXT6, and which
operation, read and/or write, require a wait state. EXT7 is
an internal register, and requires no wait state.
D1 D0
D1 D0
Wait-State EXT1
Wait-State EXT2
Wait-State EXT3
Wait-State EXT4
Wait-State EXT6
Wait-State EXT0
Wait-State EXT5
Bit14: 0 = Disabled WAIT Input Pin (default)
Bit 15: 0 = Disabled UO0, UO1 (default)
1 = Enabled P2.4 as WAIT Input Pin
1 = Enable UO0, UO1
INT0 Polarity
INT1 Polarity
INT2 Polarity
Bits [15:3]—Reserved
0 : Rising Edge (default)
1 : Falling Edge
0 : Rising Edge (default)
1 : Falling Edge
0 : Rising Edge (default)
1 : Falling Edge
00 = read (nws), write (nws)
01 = read (nws), write (nws)
10 = read (ws), write (ws)
11 = read (ws), write (ws)
nws = no wait state
ws = one wait state
DS000202-DSP0599
ZiLOG