EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 88

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

2–82
Figure 2–67. Arria GX IOE Structure
Arria GX Device Handbook, Volume 1
Logic Array
Output B
Output A
Input B
Input A
The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a
latch for a complete embedded bidirectional single data rate or DDR transfer.
Figure 2–67
(plus a latch), two output registers, and two output enable registers. The design can
use both input registers and the latch to capture DDR input and both output registers
to drive DDR outputs. Additionally, the design can use the output enable (OE)
register for fast clock-to-output enable timing. The negative edge-clocked OE register
is used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or bidirectional pins.
The IOEs are located in I/O blocks around the periphery of the Arria GX device.
There are up to four IOEs per row I/O block and four IOEs per column I/O block.
Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks
drive column interconnects.
OE
Output Register
Output Register
shows the Arria GX IOE structure. The IOE contains two input registers
D
D
Q
Q
CLK
OE Register
OE Register
D
D
Q
Q
Input Register
Input Register
D
D
Q
Q
© December 2009 Altera Corporation
Input Latch
D
ENA
Chapter 2: Arria GX Architecture
Q
I/O Structure