EP1AGX ALTERA [Altera Corporation], EP1AGX Datasheet - Page 91

• Manufacturer Part Number: EP1AGX
• Description: Section I. Arria GX Device Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–70. Signal Path Through the I/O Block
Figure 2–71. Control Signal Selection per IOE
Notes to
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection
© December 2009 Altera Corporation
multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives
the control selection multiplexers.
Figure
Dedicated I/O
Clock [7..0]
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
From Logic
To Logic
2–71:
Array
Array
Row or Column
Figure 2–70
Each IOE contains its own control signal selection for the following control signals:
oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out.
Figure 2–71
io_dataouta
io_dataoutb
io_clk[7..0]
io_dataina
io_datainb
io_ce_out
io_ce_in
io_aclr
io_sclr
io_clk
io_oe
io_oe
io_sclr
io_aclr
io_ce_out
io_ce_in
io_clk
shows the signal paths through the I/O block.
shows the control signal selection.
Selection
Control
Signal
(Note 1)
clk_in
oe
ce_in
ce_out
aclr/apreset
sclr/spreset
clk_in
clk_out
clk_out
To Other
IOEs
ce_in
ce_out
IOE
aclr/apreset
Arria GX Device Handbook, Volume 1
sclr/spreset
oe
2–85