XC4VFX20 XILINX [Xilinx, Inc], XC4VFX20 Datasheet - Page 29

• Manufacturer Part Number: XC4VFX20
• Description: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Input Delay Switching Characteristics
Table 35: Input Delay Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 36: OSERDES Switching Characteristics
DS302 (v3.2) April 10, 2008
Product Specification
Notes:
1.
2.
3.
4.
Notes:
1.
T
T
T
F
IDELAYCTRL_REF_PRECISION
T
T
Setup/Hold
Sequential Delays
Combinatorial
IDELAYRESOLUTION
IDELAYTOTAL_ERR
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
IDELAYCTRL_RPW
IDELAYPAT_JIT
T
T
T
T
T
T
T
T
T
T
T
Refer to Xilinx Application Note
This value accounts for tap 0, an anomaly in the tap chain with an average value of 34 ps.
See the “REFCLK - Reference Clock” section (specific to IDELAYCTRL) in the
Units in ps peak-to-peak per tap.
T
OSDCK_D
OSDCK_T
OSDCK_T2
OSCCK_OCE
OSCCK_S
OSCCK_TCE
OSCKO_OQ
OSCKO_TQ
OSDO_TTQ
OSCO_OQ
OSCO_TQ
OSDCK_T2
Symbol
R
Symbol
/
/
/
and T
T
T
T
OSCKD_T
OSCKD_D
/
/
OSCKD_T2
T
T
OSCKC_TCE
OSCKC_OCE
OSCKD_T2
(1)
(1)
are reported as T
(3)
XAPP707
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
SR (Reset) input Setup with respect to CLKDIV
TCE input Setup/Hold with respect to CLK
Clock to out from CLK to OQ
Clock to out from CLK to TQ
T input to TQ Out
Asynchronous Reset to OQ
Asynchronous Reset to TQ
IDELAY Chain Delay Resolution
Cumulative delay at a given tap
Reset to Ready for IDELAYCTRL
(Maximum)
REFCLK frequency
REFCLK precision
Minimum Reset pulse width
Pattern dependent period jitter in delay
chain for clock pattern
Pattern dependent period jitter in delay
chain for random data pattern (PRBS 23)
for details on IDELAY timing characteristics.
OSDCK_T
Description
/
T
OSCKD_T
Description
www.xilinx.com
in TRCE report.
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(2)
Virtex-4 FPGA User
10 ± 2
3.00
50.0
-12
200
±10
75
0
± 0.07[(tap −1) x 75 +34]
[(tap −1) x 75 +34]
Guide: Chapter 7, SelectIO Logic Resources.
–0.05
–0.16
–0.05
Speed Grade
0.35
0.43
0.35
0.45
0.01
0.67
0.45
0.01
0.41
0.41
0.56
1.14
1.14
-12
10 ± 2
3.00
50.0
-11
200
±10
75
Speed Grade
0
–0.04
–0.16
–0.04
0.42
0.52
0.42
0.53
0.02
0.80
0.53
0.02
0.49
0.49
0.65
1.37
1.37
-11
10 ± 2
3.00
50.0
-10
200
±10
75
0
–0.03
–0.16
–0.03
0.50
0.62
0.50
0.64
0.03
0.96
0.64
0.03
0.59
0.59
0.76
1.64
1.64
-10
Note (4)
Note (4)
Units
MHz
MHz
Units
ps
ps
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
29