XC3042 XILINX [Xilinx, Inc], XC3042 Datasheet - Page 17

• Manufacturer Part Number: XC3042
• Description: Logic Cell Array Families
• Manufacturer: XILINX [Xilinx, Inc]

be ready even if the master is very fast, and the slave(s)
very slow. Figure 18 shows the state sequences. At the
end of Initialization, the LCA device enters the Clear state
where it clears the configuration memory. The active Low,
open-drain initialization signal INIT indicates when the
Initialization and Clear states are complete. The LCA
device tests for the absence of an external active Low
RESET before it makes a final sample of the mode lines
and enters the Configuration state. An external wired-AND
of one or more INIT pins can be used to control configura-
tion by the assertion of the active-Low RESET of a master
mode device or to signal a processor that the LCA devices
are not yet initialized.
If a configuration has begun, a re-assertion of RESET for
a minimum of three internal timer cycles will be recognized
and the LCA device will initiate an abort, returning to the
Clear state to clear the partially loaded configuration
memory words. The LCA device will then resample RE-
SET and the mode lines before re-entering the Configura-
tion state.
A re-program is initiated.when a configured XC3000 family
device senses a High-to-Low transition and subsequent
>6 s Low level on the Done/PROG package pin, or, if this
pin is externally held permanently Low, a High-to-Low
transition and subsequent >6 s Low time on the RESET
package pin.
The LCA device returns to the Clear state where the
configuration memory is cleared and mode lines re-
sampled, as for an aborted configuration. The complete
configuration program is cleared and loaded during each
configuration program cycle.
Figure 18. A State Diagram of the Configuration Process for Power-up and Reprogram.
Power-On Delay is
2
2
14
16
Configuration
Initialization
Time Delay
Power-On
Memory
Cycles for Non-Master Mode—11 to 33 ms
Cycles for Master Mode—43 to 130 ms
Clear
INIT Output = Low
All User I/O Pins 3-Stated with High Impedance Pull-Up, HDC=High, LDC=Low
RESET
Active
No
Active RESET
Mode Pins
Low on DONE/PROGRAM and RESET
Test
2-119
Program Mode
Configuration
Length count control allows a system of multiple Logic Cell
Arrays, of assorted sizes, to begin operation in a synchro-
nized fashion. The configuration program generated by
the MakePROM program of the XACT development sys-
tem begins with a preamble of 111111110010 followed by
a 24-bit length count representing the total number of
configuration clocks needed to complete loading of the
configuration program(s). The data framing is shown in
Figure 19. All LCA devices connected in series read and
shift preamble and length count in on positive and out on
negative configuration clock edges. An LCA device which
has received the preamble and length count then presents
a High Data Out until it has intercepted the appropriate
number of data frames. When the configuration program
memory of an LCA device is full and the length count does
not yet compare, the LCA device shifts any additional data
through, as it did for preamble and length count.
When the LCA device configuration memory is full and the
length count compares, the LCA device will execute a
synchronous start-up sequence and become operational.
See Figure 20. Two CCLK cycles after the completion of
loading configuration data, the user I/O pins are enabled
as configured. As selected in MakeBits, the internal user-
logic RESET is released either one clock cycle before or
after the I/O pins become active. A similar timing selection
is programmable for the DONE/PROG output signal.
DONE/PROG may also be programmed to be an open
drain or include a pull-up resistor to accommodate wired
ANDing. The High During Configuration (HDC) and Low
During Configuration (LDC) are two user I/O pins which are
driven active while an LCA device is in its Initialization,
Clear Is
~ 200 Cycles for the XC3020—130 to 400 µs
~ 250 Cycles for the XC3030—165 to 500 µs
~ 290 Cycles for the XC3042—195 to 580 µs
~ 330 Cycles for the XC3064—220 to 660 µs
~ 375 Cycles for the XC3090—250 to 750 µs
Start-Up
PWRDWN
Inactive
No HDC, LDC
Power Down
Operational
or Pull-Up
Mode
Active RESET
PWRDWN
Operates on
User Logic
Active
X3399