CY8C20111_12 CYPRESS [Cypress Semiconductor], CY8C20111_12 Datasheet - Page 42

• Manufacturer Part Number: CY8C20111_12
• Manufacturer: CYPRESS [Cypress Semiconductor]

Glossary
Document Number: 001-53516 Rev. *H
settling time
shift register
slave device
SRAM
SROM
stop bit
synchronous
tri-state
UART
user modules
user space
V
V
watchdog timer
DD
SS
(continued)
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,
operating from Flash.
A signal following a character or block that prepares the receiving device to receive the next character or block.
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming
Interface) for the peripheral function.
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V.
A name for a power net meaning "voltage source." The most negative power supply signal.
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
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