ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 66

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

5.3.4.6
5.3.4.7
66
ATAM893-D
8-bit Pseudo MCL Mode
MCL Bus Protocol
Figure 5-43. Example of MCL Receive Dialog
In this mode, the SSI exhibits all the typical MCL operational features except for the acknowl-
edge-bit which is never expected or transmitted.
The MCL protocol constitutes a simple 2-wire bi-directional communication highway via which
devices can communicate control and data information. Although the MCL protocol can support
multi-master bus configurations, the SSI in MCL mode is intended for use purely as a master
controller on a single master bus system. So all reference to multiple bus control and bus con-
tention will be omitted at this point.
All data is packaged into 8-bit telegrams plus a trailing handshaking or acknowledge-bit. Nor-
mally the communication channel is opened with a so-called start condition, which initializes all
devices connected to the bus. This is then followed by a data telegram, transmitted by the mas-
ter controller device. This telegram usually contains an 8-bit address code to activate a single
slave device connected onto the MCL bus. Each slave receives this address and compares it
with its own unique address. The addressed slave device, if ready to receive data, will respond
by pulling the SD line low during the 9th clock pulse. This represents a so-called MCL acknowl-
edge. The controller detecting this affirmative acknowledge then opens a connection to the
required slave. Data can then be passed back and forth by the master controller, each 8-bit tele-
gram being acknowledged by the respective recipient. The communication is finally closed by
the master device and the slave device put back into standby by applying a stop condition onto
the bus.
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
SDD
ACT
SIR
SC
SD
Write STB
(tx data 1)
Start
msb
7 6 5 4 3 2 1
tx data 1
lsb
0 A
msb
7 6 5 4 3 2 1 0 A
rx data 2
lsb
4680C–4BMCU–01/05
Stop
Read SRB
(rx data 2)