ATAM893X-TKHYZ ATMEL [ATMEL Corporation], ATAM893X-TKHYZ Datasheet - Page 71

• Manufacturer Part Number: ATAM893X-TKHYZ
• Description: Flash Version for ATAR080, ATAR090/890 and ATAR092/892
• Manufacturer: ATMEL [ATMEL Corporation]

5.3.4.14
4680C–4BMCU–01/05
Serial Interface Status and Control Register (SISC)
SISC write
SISC read
MCL
RACK
TACK
SIM
IFN
SRDY
ACT
Multi-Chip Link activation
MCL = 1, multi-chip link disabled. This bit has to be set to '0' during
MCL = 0, connects SC and SD, additionally to the internal multi-chip link pads
Receive ACKnowledge status/control bit for MCL mode
RACK = 0, transmit acknowledge in next receive telegram
RACK = 1, transmit no acknowledge in last receive telegram
Transmit ACKnowledge status/control bit for MCL mode
TACK = 0, acknowledge received in last transmit telegram
TACK = 1, no acknowledge received in last transmit telegram
Serial Interrupt Mask
SIM = 1, disable interrupts
SIM = 0, enable serial interrupt. An interrupt is generated
Interrupt FuNction
IFN = 1, the serial interrupt is generated at the end of telegram
IFN = 0, the serial interrupt is generated when the SRDY goes low (i.e., buffer
Serial interface buffer ReaDY status flag
SRDY = 1,
SRDY = 0,
Transmission ACTive status flag
ACT = 1, transmission is active, i.e., serial data transfer. Stop or start conditions
ACT = 0, transmission is inactive
MCL
Bit 3
- - -
becomes empty/full in transmit/receive mode)
transactions to/from the internal EEPROM
are currently in progress.
in transmit mode: transmit buffer full
in transmit mode: transmit buffer empty
in receive mode: receive buffer empty
in receive mode: receive buffer full
RACK
TACK
Bit 2
Bit 1
ACT
SIM
SRDY
Bit 0
IFN
Primary register address: 'Hex
ATAM893-D
Reset value: 1111b
Reset value: xxxxb
71