ML67Q4002 OKI [OKI electronic componets], ML67Q4002 Datasheet - Page 15

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ML67Q4002

Manufacturer Part Number
ML67Q4002
Description
32-bit ARM-Based General-Purpose Microcontroller
Manufacturer
OKI [OKI electronic componets]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ML67Q4002-1NNNTC0AAL
Manufacturer:
ROHM
Quantity:
2 001
WDT
Functions as an interval timer or a watch dog timer.
(1) 16-bit timer
(2) Watch dog timer or interval timer mode can be selected
(3) Interrupt or reset generation.
(4) Maximum period: longer than 200 msec
PWM
This LSI contains two channels of PWM (Pulse Width Modulation) function which can change the duty cycle of
a waveform with a constant period. The PWM output resolution is 16 bits for each channel.
Serial Interface
This LSI contains four serial interface.
OKI Semiconductor
(1) UART without FIFO
(2) UART with 16bytes FIFO
(3) Synchronous serial interface
(4) I2C
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Features 16bytes FIFO in both send and receive. Uses the industry standard 16550A ACE
(Asynchronous Communication Element).
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It is a clock synchronous 8bit serial port
This is the serial port which performs data transmission, taking a synchronization per character.
Selection of various parameters, such as addition of data length, a stop bit, and a parity bit, is possible.
Based on the I2C BUS specifications. Operates as a single master device.
Asynchronous full duplex operation
Sampling Rate = Baud rate x 16sample
Character Length
Stop Bit Length
Parity
Asynchronous full duplex operation
Reporting function for all status
Modem control signals
Data length
Stop bit length
parity
selectable 1/8, 1/16 or 1/32 of HCLK frequency.
Choose LSB First or MSB First.
Choose Master / Slave Mode
Transceiver Interruption, Transceiver buffer empty interrupt
Loopback Test Function
Transmission Speed
Addressing format
Data buffer
Communication Voltage
Error Detection
Loop Back Function
Baud Rate Generation
Internal-Baud-Rate-Clock-Stop at the time of HALT Mode.
16 Byte Transmission and reception FIFO
Transmission, reception, interrupt of line status Data set and Independent FIFO control.
Error Detection
Baud Rate Generation
Communication mode
: 1 channel
: 7, 8 bit
: 1, 2 bit
: Even, Odd, none
: Parity, Framing, Over run
: ON/OFF, Parity, framing, Over run Compulsive addition
: Exclusive baud rate generator built-in (8bit counter)
: 1channel
: CTS, DCD, DSR, DTR, RI and RTS
: 5, 6, 7, 8 bit
: 1, 1.5, 2 bit
: Even, Odd, none
: Parity, Framing, Overrun
: Exclusive baud rate generator built-in
: Master transmitter /master receiver
: 100kbps (Standard mode) / 400kbps (Fast mode)
: 7 bit / 10 bit
: 1 Byte(1step)
: 2.7V to 3.3V
Independent from a bus clock
: 1channel
: 1channel
ML674001/67Q4002/67Q4003
FEDL674001-01
15/24

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