ML67Q4002 OKI [OKI electronic componets], ML67Q4002 Datasheet - Page 16

• Manufacturer Part Number: ML67Q4002
• Description: 32-bit ARM-Based General-Purpose Microcontroller
• Manufacturer: OKI [OKI electronic componets]

GPIO
42-bits parallel port (four 8-bit ports and one 10-bit port)
AD Converter
Successive approximation type AD converter.
(1) 10 bits × 4 channels
(2) Sample hold function
(3) Scan mode and select mode are supported
(4) Interrupt is generated after completion of conversion.
(5) Conversion time: 5 µs minimum.
DMAC
Two channels of direct memory access controller which transfers data between memory and memory, between
I/O and memory and between I/O and I/O.
(1) Number of channels: 2 channels
(2) Channel priority level: Fixed mode
(3) Maximum number of transfers: 65,536 times (64K times)
(4) Data transfer size: Byte (8 bits), half-word (16 bits), word (32 bits)
(5) Bus request system:
(6) DMA transfer request: Software request
(7) Interrupt request: Interrupt request is generated to CPU after the end of DMA transfers for the set
OKI Semiconductor
(1) Input/output selectable at bit level.
(2) Each bit can be used as an interrupt source.
(3) Interrupt mask and interrupt polarity can be set for all bits.
(4) The ports are configured as input, immediately after reset.
(5) Primary/secondary function of each port can be set independently.
PIOA[7:0]
PIOB[7:0]
PIOC[7:0]
PIOD[7:0]
PIOE[9:0]
number of transfer cycles or after occurrence of error.
Interrupt request signal is output separately for each channel.
Interrupt request signal output can be masked for each channel.
Roundrobin
Cycle steal mode
External request
Burst mode
Combination port
Combination port
Combination port
Combination port
Combination port
Channel priority level is always fixed (channel 0 > 1).
Priority level of the channel requested for transfer is kept lowest.
By setting the software transfer request bit inside DMAC, the CPU starts DMA
transfer.
DMA transfer is started by external request allocated to each channel.
Bus request signal is asserted for each DMA transfer cycle.
Bus request signal is asserted until all transfers of transfer cycles are complete.
.
UART
DMAC, UART(uPLAT-7B),
PWM, XA[23:19], XWR
DRAM contorol signal etc.
SSIO, I2C, External interrupt signal
ML674001/67Q4002/67Q4003
FEDL674001-01
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