STA2065A STMICROELECTRONICS [STMicroelectronics], STA2065A Datasheet - Page 16

• Manufacturer Part Number: STA2065A
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

System features introduction
Table 3.
3.5
16/20
DEEP-SLEEP
Power State
NORMAL
BACKUP
OFF
Power mode states (continued)
System wakeup and power down
Typically the system using STA2065 will never be powered off, even when the user switches
the device off using the main power switch. The main power switch works in a way that puts
the device either in Backup or in DEEP-SLEEP mode. In this state, the only blocks within
STA2065 that are powered are the RTC, PMU, PWL, SRC and the backup RAM; at system
level, only the V
The following wakeup methods are possible:
●
●
Considering the above mentioned wakeup system, while in DEEP-SLEEP and in BACKUP
state also, some dedicated IO lines must be powered:
●
●
●
●
●
●
In order to keep the external DRAM in self refresh while in DEEP-SLEEP, CKE of the DRAM
must be kept low. Since all the IOs are not powered in DEEP-SLEEP, in order to make the
self refresh working, an external pulldown resistor is needed.
The user presses a button on the unit that causes all of the main power supplies to
start. After an appropriate delay, the processor's reset line is lifted and allows the code
to start executing
The internal alarm feature triggers a dedicated signal that will cause all of the main
supplies to start. After an appropriate delay, the processor's reset line is lifted and
allows the code to start execution
POR (input)
POWEREN (output)
VDDOK and BATOK (input)
WAKE (input)
32 kHz crystal (SXTALI and SXTALO)
OSC32KOUT (output)
32 kHz
off
on
on
on
off
off
dd_on
PLL1
is powered.
off
on
Doc ID16050 Rev 1
PLL2
off
on
off
off
(typically 1.25V)
(typically 1.25V)
1.2V to 1.3V
1.2V to 1.3V
1.2V to 1.3V
V
dd_on
off
=V
V
off
dd_on
off
off
dd
Refer
Refer
1.7 to 3.6V
STA2065
IOs
3.5
3.5
off
section
section