AT43USB320A_04 ATMEL [ATMEL Corporation], AT43USB320A_04 Datasheet
AT43USB320A_04
Related parts for AT43USB320A_04
AT43USB320A_04 Summary of contents
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Features ® • AVR 8-bit RISC Microcontroller with 83 ns Instruction Cycle Time • USB Hub with One Attached and Four External Ports • USB Function with Two Programmable Endpoints • External Program Memory, 512-byte Data SRAM • ...
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Hub/Monitor/IR Chip Application Figure 1. Application Example IR XCVR REMOTE IR UNIT Pin Configurations AT43USB320A 2 IR HUB/MONITOR/IR XCVR CHIP DOWNSTREAM PORTS TO USB DEVICES 100-lead LQFP ...
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Pin Assignment Type Input O = Output B = Bi-directional V = Power Supply, Ground Pin Number Signal 1 PD2 2 PD3 3 PD4 4 PD5 5 PD6 6 PD7 7 6/12N 8 LFT 9 XTAL1 10 XTAL2 ...
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Pin Number Signal 63 CEXT2 64 DP2 65 DM2 66 DP3 67 DM3 68 DP4 69 DM4 70 PA0 71 PA1 72 PA2 73 PA3 74 PA4 75 VSS PA5 78 PA6 79 PA7 80 PB0 81 ...
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Signal Description Name Type V Power Supply/Ground CC V Power Supply/Ground SS CEXT1, 2 Power Supply/Ground XTAL1 Input XTAL2 Output LFT Input DPO Bi-directional DMO Bi-directional DP[1:4] Bi-directional DM[1:4] Bi-directional PA[0:7] Bi-directional PB[0:7] Bi-directional PC[0:7] Bi-directional PD[0:7] Bi-directional TESTN Input ...
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Figure 2. The AT43USB320A Enhanced RISC Architecture External Program Memory Instruction Register Instruction Decoder Control Lines AT43USB320A 6 Program Status and Counter Control General-purpose Registers ALU 512 x 8 SRAM 32 GPIO Lines USB Hub and Function ...
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Architectural The peripherals and features of the AT43USB320A microcontroller are similar to those of the AT90S8515, with the exception of the following modifications: Overview • External Program Memory • No EEPROM • No external data memory accesses • No Analog ...
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During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently, the stack size is only limited by the total SRAM size and ...
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X-, Y- and Z- Registers R26..R31 contain some added functions to their general-purpose usage. These reg- isters are address pointers for indirect addressing of the Data Space. The three indirect Registers address registers X, Y, and Z are defined as: ...
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SRAM Data Table 3 summarizes how the AT43USB320A SRAM Memory is organized. The lower 608 Data Memory locations address the Register file, the I/O Memory and the internal data SRAM. Memory The first 96 locations address the Register File + ...
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Table 2. SRAM Organization 1443E–USB–4/04 Register File R0 R1 R30 R31 I/O Registers $00 $01 $3E $3F AT43USB320A Data Address Space $0000 $0001 $001E $001F $0020 $0021 $005E $005F Internal SRAM $0060 $0061 $025E $045F USB Registers $1F00 $1FFE $1FFF ...
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Table 3. USB Hub and Function Registers Address $1FFD $1FFC $1FFB $1FFA $1FF9 $1FF7 $1FF5 $1FF3 $1FF2 $1FEF $1FEE $1FE7 $1FE5 $1FE4 $1FE3 $1FDF $1FDD $1FDC $1FDB $1FD7 $1FD5 $1FD4 $1FD3 $1FCF $1FCD $1FCC $1FCB $1FC7 $1FC5 $1FBC $1FBB $1FBA ...
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Table 3. USB Hub and Function Registers (Continued) Address $1FB3 $1FB2 $1FB1 $1FB0 $1FAC $1FAB $1FAA $1FA9 $1FA8 $1FA7 $1FA5 $1FA4 $1FA3 1443E–USB–4/04 Name Function HPSCR4 Hub Port 4 Status Change Register HPSCR3 Hub Port 3 Status Change Register HPSCR2 ...
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Table 4. USB Hub and Function Registers Name Address Bit 7 Bit 6 GLB_STATE $1FFB – SPRSR $1FFA – – SPRSIE $1FF9 – – UISR $1FF7 SOF INT EOF2 INT UIAR $1FF5 SOF INTACK EOF2 INTACK UIER $1FF3 SOF IE ...
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Table 4. USB Hub and Function Registers (Continued) Name Address Bit 7 Bit 6 FCAR0 $1FA5 CTL DIR DATA END FCAR1 $1FA4 CTL DIR DATA END FCAR2 $1FA3 CTL DIR DATA END 1443E–USB–4/04 Bit 5 Bit 4 Bit 3 FORCE ...
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I/O Memory The I/O space definition of the AT43USB320A is shown in the following table: Table 5. I/O Memory Space I/O (SRAM) Address $3F ($5F) $3E ($5E) $3D ($5D) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $35 ($55) $33 ...
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All AT43USB320A I/O and peripherals, except for the USB hardware registers, are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O ...
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Figure 3. USB Hardware AT43USB320A 18 Port 0 XCVR Hub Repeater Serial Interface Engine Port 5 Hub Function Interface Interface Unit Unit Data Address Control AVR Microcontroller Port 1 XCVR Port 2 XCVR Port 3 XCVR Port 4 XCVR 1443E–USB–4/04 ...
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Functional Description On-chip Power The AT43USB320A contains two on-chip power supplies that generate 3.3V with a capacity each from the 5V power input. The on-chip power supplies are intended to supply the Supply AT43USB320A internal circuit and ...
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Figure 4. Oscillator and PLL Reset and The AT43USB320A provides 22 different interrupt sources with 13 separate reset vectors, each with a separate program vector in the program memory space. Eleven of the interrupt Interrupt Handling sources share 2 interrupt ...
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The most typical and general program setup for the Reset and Interrupt Vector Addresses are: Address $000 $004 $00E $018 ; $00d start $00e $00f $010 $011 ... USB related interrupt events are routed to reset vectors 13 and 2 ...
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Figure 5. AT43USB320A Interrupt Structure SOF EOF2 EOF1 FEP2 FEP1 FEP0 RESERVED HEP0 FRMWUP RSM GLB SUSP Reset Sources The AT43USB320A has four sources of reset: • Power-on Reset – The MCU is reset when the supply voltage is below ...
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Figure 6. Reset Logic VCC POR Ckt Reset Ckt RSTN Watchdog Timer System Clock Divider Table 7. Number of Watchdog Oscillator Cycles FSTRT Programmed Unprogrammed Power-on Reset A Power-on Reset (POR) circuit ensures that the device is reset from power-on. ...
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External Reset An external reset is generated by a low-level on the RESET pin. Reset pulses longer than 200 ns will generate a reset. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset ...
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If an interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. If one or more interrupt conditions ...
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General Interrupt Mask Register – GIMSK Bit $3B ($5B) Read/Write Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), ...
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Timer/Counter Interrupt Mask Register – TIMSK Bit $39 ($59) Read/Write Initial Value • Bit 7 – TOIE1: Timer/Counter1 Overflow Interrupt Enable When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter1 ...
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Timer/Counter Interrupt Flag Register – TIFR Bit $38 ($58) Read/Write Initial Value • Bit 7 – TOV1: Timer/Counter1 Overflow Flag The TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by the hardware when executing the ...
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External Interrupts The external interrupts are triggered by the INT0 and INT1 pins. Observe that, if enabled, the INT0/INT1 interrupt will trigger even if the INT0/INT1 pins are configured as outputs. This fea- ture provides a way of generating a ...
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MCU Control Register – MCUCR Bit $35 ($55) Read/Write Initial Value • Bit 7, 6 – Res: Reserved Bits • Bit 5 – SE: Sleep Enable The SE bit must be set (1) to make the MCU enter the sleep ...
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USB Interrupt The USB interrupts are described below. Sources Table 10. USB Interrupt Sources Interrupt SOF Received EOF2 Function EP0 Interrupt Function EP1 Interrupt Function EP2 Interrupt Hub EP0 Interrupt FRWUP GLB SUSP RSM All interrupts have individual enable, status, ...
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USB Endpoint An assertion or activation of one or more bits in the endpoint's Control and Status Register triggers the endpoint interrupts. These triggers are different for control and non-control end- Interrupt Sources points as described in the table below. ...
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USB Interrupt Acknowledge Register – UIAR Bit $1FF5 Read/Write Initial Value • Bit 7 – SOF INTACK: Start of Frame Interrupt Acknowledge The microcontroller firmware writes this bit to clear the SOF INT bit. • Bit 6 ...
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USB Interrupt Enable Register – UIER Bit $1FF3 Read/Write Initial Value • Bit 7 – SOF IE: Enable Start of Frame Interrupt When the SOF IE bit is set (1), the Start of Frame Interrupt is enabled. • Bit 6 ...
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Suspend/Resume Interrupt Enable Register – SPRSIE Bit $1FF9 Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved and are always read as zeros. • Bit 3 – BUS INT EN: USB Reset Interrupt Enable When ...
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AVR Register Set Status Register and Stack Pointer Status Register – SREG Bit $3F ($5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The global interrupt enable bit must be set (one) for the interrupts to be ...
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Stack Pointer Register – SP Bit $3E ($5E) $3D ($5D) Read/Write Initial Value The Stack Pointer points to the data SRAM stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be ...
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Timer/Counters The AT43USB320A provides two general-purpose Timer/Counters - one 8-bit T/C and one 16- bit T/C. The Timer/Counters have individual prescaling selection from the same 10-bit prescal- ing timer. Both Timer/Counters can either be used as a timer with an ...
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The 8-bit Timer/Counter0 can select clock source from CK, prescaled external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Timer/Counter0 Register (TCCR0). The overflow status flag is found ...
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Timer/Counter0 Control Register – TCCR0 Bit $33 ($53) Read/Write Initial Value • Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and always read as zero. • Bits – CS02, CS01, CS00: ...
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Timer/Counter1 Figure 11. Timer/Counter1 Block Diagram T/C1 OVERFLOW IRQ TIMER INT. MASK REGISTER (TIMSK T/C1 INPUT CAPTURE REGISTER (ICR1) 15 TIMER/COUNTER1 (TCNT1 16-BIT COMPARATOR 8 15 TIMER/COUNTER1 OUTPUT COMPARE REGISTER A 1443E–USB–4/04 T/C1 COMPARE T/C1 ...
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The 16-bit Timer/Counter1 can select clock source from CK, prescaled external pin. In addition, it can be stopped as described in the specification for the Timer/Counter1 Control Timer/Counter1 Registers (TCCR1A and TCCR1B). The different status flags ...
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Timer/Counter1 Control Register A – TCCR1A Bit $2F ($4F) Read/Write Initial Value • Bits 7, 6 – COM1A1, COM1A0: Compare Output Mode1A, Bits 1 and 0 The COM1A1 and COM1A0 control bits determine any output pin action following a compare ...
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Timer/Counter1 Control Register B – TCCR1B Bit $2E ($4E) Read/Write Initial Value • Bit 7 – ICNC1: Input Capture1 Noise Canceler (4 CKs) When the ICNC1 bit is cleared (zero), the input capture trigger noise canceler function is dis- abled. ...
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Table 15. Clock 1 Prescale Select (Continued) CS12 The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the 12 MHz system clock. If the external pin modes are used for Timer/Counter1, transitions ...
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Timer/Counter1 – TCNT1H and TCNT1L Bit $2D ($4D) $2C ($4C) Read/Write Initial Value This 16-bit register contains the prescaled value of the 16-bit Timer/Counter1. To ensure that both the high and low bytes are read and written simultaneously when the ...
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Timer/Counter1 Output Compare Register – OCR1AH and OCR1AL Bit $2B ($4B) $2A ($4A) Read/Write Initial Value Timer/Counter1 Output Compare Register – OCR1BH and OCR1BL Bit $29 ($49) $28 ($48) Read/Write Initial Value The output compare registers are 16-bit read/write registers. ...
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Timer/Counter1 Input Capture Register – ICR1H and ICR1L Bit $25 ($45) $24 ($44) Read/Write Initial Value The input capture register is a 16-bit read-only register. When the rising or falling edge (according to the input capture edge setting - ICES1) ...
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Table 17. Compare1 Mode Select in PWM Mode COM1X1 Note: Note that in the PWM mode, the 10 least significant OCR1A/OCR1B bits, when written, are transferred to a temporary location. They are latched when Timer/Counter1 reaches the value TOP. This ...
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TOP value, making a one-period PWM pulse. Table 18. PWM Outputs OCR1X = $0000 or Top COM1X1 Note: In PWM ...
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Watchdog Timer Control Register – WDTCR Bit $21 ($41) Read/Write Initial Value • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the AT43USB320A and will always read as zero. • Bit 4 – WDTOE: Watch Dog ...
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Serial Peripheral The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the AT43USB320A a nd peripheral devices or betwee n several AVR d evice s. The Interface (SPI) AT43USB320A SPI features include the following: • Full-duplex, 3-wire Synchronous ...
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The interconnection between master and slave CPUs with SPI is shown in Figure 16. The PB7(SCK) pin is the clock output in the master mode and is the clock input in the slave mode. Writing to the SPI data register ...
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SS Pin Functionality When the SPI is configured as a master (MSTR in SPCR is set), the user can determine the direction of the SS pin configured as an output, the pin is a general output pin ...
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Figure 18. SPI Transfer Format with CPHA = 1 and DORD = 0 SCK Cycle # (For Reference) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (From Master) MISO * (From Slave) SS (To Slave) Note: * Not defined, ...
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SPI Control Register – SPCR Bit $0D ($2D) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR register is set and the global ...
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SPI Status Register – SPSR Bit $0E ($2E) Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF bit is set (one) and an interrupt is generated if SPIE in SPCR ...
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Data A block schematic of the UART transmitter is shown in Figure 19. Transmission Data transmission is initiated by writing the data to be transmitted to the UART I/O Data Register, UDR. Data is transferred from UDR to the Transmit ...
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Figure 19. UART Transmitter Data Reception Figure 20 shows a block diagram of the UART Receiver. The receiver front-end logic samples the signal on the RXD pin at a frequency 16 times the baud rate. While the line is idle, ...
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When UDR is read, the Receive Data register is accessed, and when UDR is written, the Transmit Data register is accessed. If, after having received a character, the UDR register ...
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UART Control UART I/O Data Register UDR – Bit $0D ($2C) Read/Write Initial Value The UDR register is actually two physically separate registers sharing the same I/O address. When writing to the register, the UART Transmit Data register is written. ...
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When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal is used, the UART Data Register Empty Interrupt ...
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Baud Rate The baud rate generator is a frequency divider that generates baud rates according to the fol- lowing equation: Generator BAUD = SYSCLK/16(UBRR + 1) • BAUD = Baud rate • SYSCLK = 16 MHz • UBRR = Contents ...
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The Port A Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. The port pins have no selectable pull-up resistors. Port A Data Register – PORTA Bit $1B ($3B) Read/Write ...
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Three I/O memory address locations are allocated for the Port B, one each for the Data Regis- ter - PORTB, $18($38), Data Direction Register (DDRB), $17($37) and the Port B Input Pins (PINB), $16($36). The Port B Input Pins address ...
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Port B Data Register – PORTB Bit $18 ($38) Read/Write Initial Value Port B Data Direction Register – DDRB Bit $17 ($37) Read/Write Initial Value Port B Input Pins Address – PINB Bit $16 ($36) Read/Write Initial Value The Port ...
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Port C Port 8-bit bi-directional I/O port with push-pull outputs. The Port C output buffers can sink 4 mA Three I/O memory address locations are allocated for the Port C, one each for the Data Regis- ter ...
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Port D Port 8-bit bi-directional I/O port. Its output buffers can sink or source 2 mA. Three I/O memory address locations are allocated for the Port D, one each for the Data Regis- ter - PORTD, $12($32), ...
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Port D as General PDn, General I/O Pin: The DDDn bit in the DDRD register selects the direction of this pin. If Digital I/O DDDn is set (one), PDn is con-figured as an output pin. If DDDn is cleared (zero), ...
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Retries and data toggles are performed automatically by the USB hardware. When the IN endpoint is not ready to send data, in the case where the microcontroller has not filled the FIFO, it ...
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The following state diagram shows how the various state transitions are triggered. Additional decision making may take place within the response states to determine the next expected state. Unmarked arcs represent transitions that trigger immediately following completion of the response ...
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The following information describes how the AT43USB320A’s USB hardware and firmware operates during a control transfer between the host and the hub’s or function’s control endpoint. Legend: Idle State This is the default state from power-up. Setup Response State The ...
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No-data Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet until receiving an ACK from the host, then asserts a TX_COMPLETE interrupt token from ...
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Control Read Status The Function Interface Unit receives an OUT token from the Host with a zero length DATA1 Response State packet. The FIU responds with a NAK until TX_COMPLETE is cleared. The FIU will then ACK the retried OUT ...
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Control Write Status The Function Interface Unit receives an IN token from the Host. The FIU responds with a zero Response State length DATA1 packet, retrying until it receives an ACK back from the Host. The FIU then asserts a ...
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Interrupt/Bulk IN The firmware must first condition the endpoint through the Endpoint Control Register, Transfers at Function FENDP1/2_CNTR: Endpoint Set endpoint direction: set EPDIR Set interrupt or bulk: EPTYPE = Enable endpoint: set EPEN The Function Interface ...
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USB Registers The following sections describe the registers of the AT43USB320A’s USB hub and function units. Reading a bit for which the microcontroller does not have read access will yield a zero value result. Writing to a bit for which ...
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Function Address The USB function contains an address register that contains the function address assigned by Register – FADDR the host. This Function Address Register must be programmed by the microcontroller once it has received a SET_ADDRESS request from the ...
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Function Endpoint 1, 2 Control Register – FENDP1,2_CR Bit $1FE4 $1FE3 Read/Write Initial Value • Bit 7 – EPEN: Endpoint Enable 0 = Disable endpoint 1 = Enable endpoint • Bit 6..4 – Reserved These bits are reserved in the ...
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Hub Endpoint 0 Data Register – HDR0 Function Endpoint 0..2 Data Register – FDR0..2 Bit $1FD7 $1FD5 $1FD4 $1FD3 Read/Write Initial Value This register is used to read data from or to write data to the Hub Endpoint 0 FIFO. ...
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Hub Endpoint 0 Byte Count Register – HBYTE_CNT0 Function Endpoint 0..2 Byte Count Register – FBYTE_CNT0..2 The contents of these registers stores the number of bytes to be sent or that was received by USB Hub and Function endpoints. This ...
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Hub Endpoint 0 Service Routine Register – HCSR0 Function Endpoint 0 Service Routine Register – FCSR0 Function EP0 $1FDF Function EP0 $1FDD Read/Write Initial Value • Bit 7..4 – Reserved These bits are reserved in the AT43USB320A and will read ...
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Hub Endpoint 0 Control and Acknowledge Register – HCAR0 Function Endpoint 0 Control and Acknowledge Register – FCAR0 Bit Hub EP0 $1FA7 Function EP0 $1FDD Read/Write Initial Value • Bit 7 – DIR: Control transfer direction It is set by ...
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Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com- plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the microcontroller. • Bit ...
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Function Endpoint 1, 2 Control and Acknowledge Register – FCAR1, 2 Bit Function EP1 $1FA4 Function EP2 $1FA3 Read/Write Initial Value • Bit 7 – Reserved This bit is reserved in the AT43USB320A and will read as zero. • Bit ...
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USB Hub The hub in a USB system provides for the electrical interface between USB devices and the host. The major functions that the hub must supports are: • Connectivity • Power management • Device connect and disconnect • Bus ...
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Hub General Registers Global State Register – GLB_STATE Bit $1FFB Read/Write Initial Value • Bit 7...5 – Reserved Bits These bits are reserved in the AT43USB320A and will read as zeros. • Bit 4 – SUSP FLG: Suspend Flag This ...
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Hub Status Register In the AT43USB320A overcurrent detection and port power switch control output processing is done in firmware. The hardware is designed so that various types of hubs are possible just through firmware modifications. 1. Hub local power status, ...
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Hub Port Control Register – HPCON Bit $1FC5 Read/Write Initial Value • Bit 7 – Reserved This bits is reserved in the AT43USB320A and will read as zero. • Bit 6..4 – HPCON2..0: Hub Port Control Command These bits are ...
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These bits define which port is being addressed for the command defined by bits [2:0]. AT43USB320A 90 Bit2 Bit1 Bit0 Port addresses 1 Port 5 0 Port 4 1 Port ...
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Selective Suspend The host can selectively suspend and resume a port through the Set Port Feature and Resume (PORT_SUSPEND) and Clear Port Feature (PORT_SUSPEND). A port enters the suspend state after the microcontroller interprets the suspend request and sets the ...
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Hub Port Status The bits in this register are used by the microcontroller firmware when reporting a port's status Register through the Port Status Field, wPortStatus . Bits 3 (POCI) and 5 (PPSTAT) are used by the USB hardware and ...
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Port is enabled Set and cleared by the hardware as controlled through Port Control register. • Bit 0 – PCSTAT: Port Connect Status device on this port 1 = Device present on this port Set ...
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Hub Port Status Change Register – PSCR1..3 Bit Port1 $1FB0 Port2 $1FB1 Port3 $1FB2 Port4 $1FB3 Port5 $1FB4 Read/Write Initial Value The microcontroller firmware uses the bits in this register to monitor when a port status change has occurred, which ...
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Bit 1 – PESC: Port Enable/Disable Status Change change has occurred on Port Enable/Disable Status 1 = Port Enable/Disable status has changed Set by hardware due to babble, physical disconnect or overcurrent except for Port 5 ...
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Figure 22. Port Power Management BUS_POWER GND Suspend and The AT43USB320A enters suspend only when requested by the USB host through bus inac- tivity for at least 3 ms. The USB hardware would detect this request, sets the GLB_SUSP bit ...
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The microcontroller starts executing where it left off and services the interrupt. As part of the ISR, the firmware clears the GLB SUSP bit. At completion of RESUME signaling, the USB hardware sets the Port Suspend ...
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Remote Wake-up, The hardware detects a connect/disconnect/port resume and propagates resume signaling Downstream Ports upstream. Finally, the hardware enables the oscillator and asserts the RSM interrupt. 1. Connect/disconnect/port resume detected 2. Propagate resume signaling 3. Enable Oscillator 4. Set RSM ...
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Selective Suspend, Embedded Function Selective Resume, Embedded Function 6. Send updated port status at next IN to endpoint1 1443E–USB–4/04 Hardware 1. Set Port Feature PORT_SUSPEND decoded 2. Disable Port 5’s endpoints 3. Set GPIO to low power state if required ...
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Electrical Specification Absolute Stresses beyond those listed below may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions Maximum Ratings beyond those indicated in the ...
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Table 31. USB Signals: DPx, DMx Symbol IHZ OL1 V OH1 V CRS V IN Table 32. PA, PB, PC, PD Symbol V OL2 V OH2 V IL2 V IH2 ...
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Table 33. Oscillator Signals: XTAL1, XTAL2 Symbol CX1 CX2 C12 Note: AC Characteristics Table 34. USB Driver Characteristics, Full Speed Operation Symbol TR TF TRFM ZDRV Note: Figure 23. Full-speed Load Table 35. ...
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Figure 24. Low-speed Downstream Port Load Table 36. USB Source Timings, Full-speed Operation Symbol Parameter (1) TDRATE Full Speed Data Rate (1) TFRAME Frame Interval TRFI Consecutive Frame Interval Jitter TRFIADJ Consecutive Frame Interval Jitter Source Diff Driver Jitter TDJ1 ...
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Figure 25. Differential Data Jitter Figure 26. Differential-to-EOP Transition Skew and EOP Width Figure 27. Receiver Jitter Tolerance AT43USB320A 104 T PERIOD Crossover Differential Points Data Lines Consecutive Transitions N PERIOD XJR1 Paired Transitions N PERIOD ...
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Table 37. Hub Timings, Full-speed Operation Symbol THDD2 THDJ1 THDJ2 TFSOP TFEOPD TFHESK Table 38. Hub Timings, Low-speed Operation Symbol TLHDD TLHDJ1 TLHDJ2 TLUHJ1 TLUHJ2 TSOP TLEOPD TLHESK 1443E–USB–4/04 Parameter Condition Hub Differential Data Delay without cable Hub Diff Driver ...
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Table 39. Hub Event Timings Symbol TDCNN TDDIS TURSM TDRST TDSPDEV TURLK TURLSEO TURPSEO TUDEOP AT43USB320A 106 Parameter Condition Time to detect a downstream port connect event Time to detect a disconnect event on downstream port Awake Hub Suspended Hub ...
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Figure 28. Hub Differential Delay, Differential Jitter and SOP Distortion Upstream End of Cable V SS Differential Data Lines Downstream Hub Delay With Cable Figure 29. Hub EOP Delay and EOP Skew Upstream End of Cable V ...
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Table 40. External Program Memory Read Timing Symbol Parameter t Address to Output Delay ACC t CEN to Output Delay CEN t CEN to Output Float DF t Output Hold from CEN or Address, whichever occurred first OH Figure 30. ...
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Ordering Information Ordering Code AT43USB320A -AC 1443E–USB–4/04 Package 100 LQFP AT43USB320A Operation Range Commercial (0°C to 70°C) 109 ...
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Packaging Information 100AA – LQFP PIN 1 PIN 1 IDENTIFIER e C 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm ...
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Errata Sheet Errata (All Date Codes): Missed Watchdog Timer Reset Problem There is a synchronization problem between the watchdog clock and the AVR clock. Even though the clock inputs to both the watchdog timer and the AVR core are generated ...
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Change Log Doc. Rev. 1443E AT43USB320A 112 Comments • Data Correction: timeout period data in Table 19 on page 51. • Information Change: UART does not support a 9-bit data mode. Changes were made to “Data Reception” on page 59, ...
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Table of Features ................................................................................................. 1 Contents Description ............................................................................................ 1 Hub/Monitor/IR Chip Application......................................................... 2 Pin Configurations................................................................................ 2 Pin Assignment ................................................................................... 3 Architectural Overview......................................................................... 7 The General-purpose Register File ..................................................... 8 Functional Description ....................................................................... 19 AVR Register Set ................................................................................ 36 Timer/Counters ................................................................................... ...
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Timer/Counter0........................................................................................... 39 16-bit Timer/Counter1......................................................................................... 41 16-bit Timer/Counter1 Operation ........................................................................ 42 Watchdog Timer ................................................................................................. 50 Serial Peripheral Interface (SPI) ......................................................................... 52 UART.................................................................................................... 57 Data Transmission.............................................................................. 58 Data Reception.................................................................................... 59 UART Control ...................................................................................... 61 Baud Rate Generator.......................................................................... 63 I/O-Ports............................................................................................... 63 ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...