AT43USB320A_04 ATMEL [ATMEL Corporation], AT43USB320A_04 Datasheet - Page 62

• Manufacturer Part Number: AT43USB320A_04
• Description: Full-speed USB Microcontroller with an Embedded Hub
• Manufacturer: ATMEL [ATMEL Corporation]

UART Control
Register
62
–
AT43USB320A
UCR
When the UDRIE bit in UCR is set, the UART Transmit Complete interrupt to be executed as
long as UDRE is set. UDRE is cleared by writing UDR. When interrupt-driven data transmittal
is used, the UART Data Register Empty Interrupt routine must write UDR in order to clear
UDRE, otherwise a new interrupt will occur once the interrupt routine terminates. UDRE is set
(one) during reset to indicate that the transmitter is ready.
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incoming
character is zero. The FE bit is cleared when the stop bit of received data is one.
• Bit 3 – OR: Overrun
This bit is set if an Overrun condition is detected, i.e., when a character already present in the
UDR register is not read before the next character has been shifted into the Receiver Shift reg-
ister. The OR bit is buffered, which means that it will be set once the valid data still in UDRE is
read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
• Bits 2...0 – Res: Reserved Bits
These bits are reserved bits in the AT43USB320A and will always read as zero.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Complete
Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Complete
Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data Register
Empty Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 4 – RXEN: Receiver Enable
This bit enables the UART receiver when set (one). When the receiver is disabled, the TXC,
OR and FE status flags cannot become set. If these flags are set, turning off RXEN does not
cause them to be cleared.
• Bit 3 – TXEN: Transmitter Enable
This bit enables the UART transmitter when set (one). When disabling the transmitter while
transmitting a character, the transmitter is not disabled before the character in the shift register
plus any following character in UDR has been completely transmitted.
• Bit 2 ..0 – RES: Reserved Bits
These bits are the reserved bits of the AT43USB320A.
Read/Write
Initial value
$0A ($2A)
Bit
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
2
-
R
1
1
-
R/W
0
0
-
1443E–USB–4/04
UCR