STPCI0180BTC3 STMICROELECTRONICS [STMicroelectronics], STPCI0180BTC3 Datasheet
STPCI0180BTC3
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PC Compatible Embedded Microprocessor POWERFUL X86 PROCESSOR 64-BIT BUS ARCHITECTURE 64-BIT 66MHz DRAM CONTROLLER SVGA GRAPHICS CONTROLLER 135MHz RAMDAC UMA ARCHITECTURE TFT DISPLAY CONTROLLER PCI MASTER / SLAVE / ARBITER LOCAL BUS INTERFACE ISA (MASTER/SLAVE) INTERFACE -INCLUDING THE IPC PC-CARD ...
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STPC INDUSTRIAL X86 Processor core Fully static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back capability. Parallel processing integral floating point unit, with automatic ...
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ISA master/slave Generation of the ISA clock from either 14.318MHz oscillator clock or system clock Programmable extra wait state for ISA cycles Supports I/O recovery time for back to back I/O cycles. Fast Gate A20 and Fast reset. Supports the ...
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GENERAL DESCRIPTION 1 GENERAL DESCRIPTION At the heart of the STPC Industrial is an advanced 64-bit processor block, dubbed the 5ST86. The 5ST86 includes a powerful x86 processor core along with a 64-bit DRAM controller, advanced 64-bit accelerated graphics and ...
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The need for system configuration jumpers is eliminated by providing address mapping support for PCMCIA 2.0 / JEIDA 4.1 PC-Card memory together with address windowing support for I/O space. Selectable interrupt steering from PC-Card to internal system bus is also ...
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GENERAL DESCRIPTION Figure 1.1. Functionnal description. x86 Core Host I/F Local Bus I/F PCI m/s GE VGA CRTC DRAM I/F 6/55 Serial 2 // Port ISA BUS ISA IPC m/s 82C206 PCI m/s PCI BUS PCMCIA CARDBUS HW Cursor TFT ...
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Figure 1.2. PCI, PCMCIA & CARDBUS modes: PCI BUS PCI m/s PCI BUS PCI m/s PCI BUS PCI m/s GENERAL DESCRIPTION PCMCIA CARDBUS PCMCIA CARDBUS PCMCIA CARDBUS Issue 1.1 7/55 ...
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GENERAL DESCRIPTION Figure 1.3. Local Bus and ISA bus modes: ISA BUS Local Bus I/F ISA BUS Local Bus I/F Figure 1.4. TFT in normal (serial 1 available) and extended modes (serial 1 unavailable). Kbd Serial 1 Mouse 9-bit mode ...
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Figure 2. Typical PC oriented Application Super I/O Flash ISA MUX IRQ MUX DMA.REQ STPC Industrial DMA.ACK DMUX PCI 4x 16-bit EDO DRAMs IDE Serial Ports Parallel Port Floppy RTC Issue 1.1 GENERAL DESCRIPTION Monitor SVGA TFT Keyboard Mouse 9/55 ...
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GENERAL DESCRIPTION Figure 3. Typical Embedded Application STPC Local Bus SRAM Flash STPC Industrial PC-Card PCMCIA CARDBUS 4x 16-bit EDO DRAMs 10/55 I/O Peripheral MUX IRQ Issue 1.1 Monitor SVGA TFT Keyboard Mouse Serial Ports Parallel Port ...
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STRAP OPTION This chapter defines the STPC Industrial Strap Options and their location Memory Data Refer to Designation Lines MD0 - MD1 - MD2 DRAM Bank 1 MD3 MD4 MD5 DRAM Bank 0 MD6 MD7 MD8 - MD9 - ...
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STRAP OPTION Memory Data Refer to Designation Lines PCMCIA or PCI i Local Bus or ISA i Key Board & Mouse Serial Port ...
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STRAP REGISTER 1 INDEX 4BH (STRAP1) Bits 7-0, This register reflect the status of pins MD[15:8] respectively. They are expected to be connected on the system board to the SIMM configuration pins as follows: Bit Sampled Bit 7 Bits ...
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STRAP OPTION 2.1.4 STRAP REGISTER 3 INDEX 3CH (STRAP3) Bits 7-0 of this register reflect the status of pins MD[47:40] respectively. They are use by the chip as follows: Bit 7-6, Reserved. Bit 5, UART2 internal or external. This bit ...
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STRAP REGISTER 4 INDEX 3Dh (STRAP4) Bits 5-0 of this register reflect the status of pins MD[53:48] respectively. They are use by the chip as follows: Bits 7-5 Reserved. Bit 4, y.y V present on board. This bit reflects ...
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STRAP OPTION 2.1.6 HCLK PLL STRAP REGISTER 0 INDEX 5FH (HCLK_STRAP0) Bits 5-0 of this register reflect the status of pins MD[26:21] respectively. They are use by the chip as follows: Bits 7-6, Reserved. Bits 5-3, These pins reflect the ...
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PIN DESCRIPTION 3.1. INTRODUCTION The STPC Industrial integrates most of the func- tionalities of the PC architecture. Therefore, many of the traditional interconnections between the host PC microprocessor and the peripheral devic- es are totally internal to the STPC ...
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PIN DESCRIPTION Table 3-2. Definition of Signal Pins Signal Name Dir BASIC CLOCKS AND RESETS SYSRSTI#* I SYSRSTO#* O XTALI I XTALO O PCI_CLKI* I PCI_CLKO O ISA_CLK, ISA_CLK2X O CLK14M O HCLK* I/O DEV_CLK* O GCLK2X I/O DCLK I/O ...
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Table 3-2. Definition of Signal Pins Signal Name Dir RMRTCCS#* O GPIOCS#* I/O IRQ_MUX[3:0]* I DACK_ENC[2:0]* O DREQ_MUX[1:0]* I TC* O KEYBOARD & MOUSE INTERFACE KBDATA*, MDATA* I KBCLK*, MCLK* O SERIAL INTERFACE (SERIAL 1 COMBINED WITH TFT INTERFACE / ...
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PIN DESCRIPTION Table 3-2. Definition of Signal Pins Signal Name Dir CE1#*, CE2#* O VS1#*, VS2#* I VCC5_EN* O VCC3_EN* O VPP_PGM* O VPP_VCC* O CARDBUS INTERFACE (COMBINED WITH PCI / PCMCIA) CCLKRUN* I/O CRST#* O CSTSCHG#* I CAD[31:0]* I/O ...
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Table 3-2. Definition of Signal Pins Signal Name Dir MONITOR INTERFACE RED, GREEN, BLUE O VSYNC* I/O HSYNC* I/O VREF_DAC I RSET I COMP I DDC[1:0]* I/O SCL / DDC[1]* I/O SDA / DDC[0]* I/O TFT INTERFACE (COMBINED WITH SERIAL ...
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PIN DESCRIPTION 3.2. SIGNAL DESCRIPTIONS 3.2.2 BASIC CLOCKS AND RESETS SYSRSTI# System Reset/Power good. This input is low when the reset switch is depressed. Other- wise, it reflects the power supply’s power good signal. PWGD is asynchronous to all clocks, ...
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RAS#[3:0] Row Address Strobe. There are 4 ac- tive low row address strobe outputs, one each for each bank of the memory. Each bank contains 4 or 8-Bytes of data. The memory controller allows half of a bank (4-Bytes) to ...
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PIN DESCRIPTION SMEMR# System Memory Read. The STPC In- dustrial generates SMEMR# signal of the ISA bus only when the address is below one MByte or the cycle is a refresh cycle. SMEMW# System Memory Write. The STPC In- dustrial ...
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IPC (Combined with Serial Interface) DACK_ENC[2:0] DMA Acknowledge. These are the ISA bus DMA acknowledge signals. They are encoded by the STPC Industrial before output and should be decoded externally using ISACLK and ISACLKX2 as the control strobes. DREQ_MUX[1:0] ...
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PIN DESCRIPTION 3.2.10 PCMCIA INTERFACE (Combined with PCI / Cardbus) RESET Card Reset. This output forces a hard reset Card. A[25:0] Address Bus. These are the 25 low bits of the system address bus of the PCMCIA ...
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CARDBUS INTERFACE (Combined with PCI / PCMCIA) For card bus pinouts, refer to the PCI pinout. 3.2.12 PCI INTERFACE AD[31:0] PCI Address/Data. This is the 32-bit multiplexed address and data bus of the PCI. This bus is driven by ...
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PIN DESCRIPTION HSYNC Horizontal Synchronisation Pulse. This is the horizontal synchronization signal from the VGA controller. VREF_DAC DAC Voltage reference. This pin is an input driving the digital to analog converters. This allows an external voltage reference source to be ...
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Table 3-3. Signals sharing the same pin ISA BUS / IPC LOCAL BUS LA[23:22] FCS#[0], PRD#[1] LA[21:20] PA[21:20] LA[19:17] PRD#[0], PWR#[1:0] SA[19:1] PA[19:1] SA[0] PRDY# SD[15:0] PD[15:0] BHE# FCS#[1] MEMR#, MEMW# IOCS[3:2] SMEMR#, SMEMW# IOCS[1:0] GPIOCS# IOCHRDY IOR# IOW# MASTER# ...
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PIN DESCRIPTION PCI CARDBUS AD[19] CAD[19] AD[18] CAD[18] AD[17] CAD[17] AD[16] CAD[16] AD[15] CAD[15] AD[14] CAD[14] AD[13] CAD[13] AD[12] CAD[12] AD[11] CAD[11] AD[10] CAD[10] AD[9] CAD[9] AD[8:0] CAD[8:0] BE[3] CBE[3] BE[2] CBE[2] BE[1] CBE[1] BE[0] CBE[0] FRAME# CFRAME# TRDY# CTRDY# ...
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Table 3-4. Pinout. Pin # Pin name C4 SYSRSTI# A3 SYSRSTO# AB25 XTALI AB23 XTALO G25 PCI_CLKI H23 PCI_CLKO B20 ISA_CLK A20 ISA_CLK2X AC26 CLK14M H26 HCLK J26 DEV_CLK AC15 GCLK2X AD16 DCLK AE13 MA[0] AC12 MA[1] AF13 MA[2] AD12 ...
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PIN DESCRIPTION Pin # Pin name D3 SA[18] / PA[18] D2 SA[19] / PA[19] P2 SD[0] / PD[0] M3 SD[1] / PD[1] N1 SD[2] / PD[2] M4 SD[3] / PD[3] N2 SD[4] / PD[4] L3 SD[5] / PD[5] M1 SD[6] ...
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Pin # Pin name B21 VPP_PGM A22 VPP_VCC AD4 RED AF4 GREEN AE5 BLUE AF3 VSYNC AE4 HSYNC AF5 VREF_DAC AE6 RSET AF6 COMP AE3 SDA / DDC[1] AF2 SCL / DDC[0] AE7 B[2] AF7 G[2] AD7 R[2] AE8 B[3] ...
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ELECTRICAL SPECIFICATIONS 4 ELECTRICAL SPECIFICATIONS 4.1 INTRODUCTION The electrical specifications in this chapter are valid for the STPC Industrial. 4.2 ELECTRICAL CONNECTIONS 4.2.1 Power/Ground Connections/Decoupling Due to the high frequency of operation of the STPC Industrial necessary to ...
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DC CHARACTERISTICS Table 4-2. DC Characteristics Recommended Operating conditions : VDD = 3.3V Symbol Parameter V Operating Voltage DD P Supply Power Internal Clock (Note 1) CLK V DAC Voltage Reference DAC V Output Low Voltage ...
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ELECTRICAL SPECIFICATIONS Table 4-4. Drive Level and Measurement Points for Switching Characteristics Symbol V REF V IHD V ILD Note: Refer to Figure 4-1. Figure 4-1. Drive Level and Measurement Points for Switching Characteristics CLK: B Valid OUTPUTS: Output n ...
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Table 4-5. DRAM Bus AC Timing Name Parameter t1 HCLK to RAS#[3:0] valid t2 HCLK to CAS#[7:0] bus valid t3 HCLK to MA[11:0] bus valid t4 HCLK to MWE# valid t5 HCLK to MD[63:0] bus valid t6 MD[63:0] Generic setup ...
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ELECTRICAL SPECIFICATIONS Table 4-9. PCMCIA Interface AC Timing Name Parameters t24 Input setup to ISACLK2X t25 Input hold from ISACLK2X t28 ISACLK2X to IORD t29 ISACLK2X to IORW t30 ISACLK2X to AD[25:0] t31 ISACLK2X to OE# t32 ISACLK2X to WE# ...
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Table 4-13. Local Bus Interface AC Timing Name Parameters t46 PRDY# Input hold to HCLK t47 PD[15:0] Input hold to HCLK t48 PRDY# Input setup to HCLK t49 PD[15:0] Input setup to HCLK t50 HCLK to PA bus t51 HCLK ...
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ELECTRICAL SPECIFICATIONS 40/55 Issue 1.1 ...
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MECHANICAL DATA 5.1 388-PIN PACKAGE DIMENSION The pin numbering for the STPC 388-pin Plastic BGA package is shown in Figure 5-1. Figure 5-1. 388-Pin PBGA Package - Top View ...
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MECHANICAL DATA Figure 5-2. 388-pin PBGA Package - PCB Dimensions A1 Ball Pad Corner A Table 5-1. 388-pin PBGA Package - PCB Dimensions Symbols Min A 34.95 35.00 B 1.22 C 0.58 D 1.57 E 0.15 F 0.05 G 0.75 ...
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Figure 5-3. 388-pin PBGA Package - Dimensions C Solderball A Table 5-2. 388-pin PBGA Package - Dimensions Symbols Min A 0.50 B 1.12 C 0.60 D 0.52 E 0. Solderball after collapse G mm Typ ...
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MECHANICAL DATA 5.2 388-PIN PACKAGE THERMAL DATA 388-pin PBGA package has a Power Dissipation Capability of 4.5W which increases to 6W when used with a Heatsink. Figure 5-4. 388-Pin PBGA structure Signal layers Figure 5-5. Thermal dissipation without heatsink Board ...
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Figure 5-6. Thermal dissipation with heatsink Board Ambient Rca Case Rjc Board Junction Rjb Board Rba Ambient Board dimensions: Junction - 10 12 layers (2 for signals, 1 GND, 1VCC The PBGA is ...
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MECHANICAL DATA 46/55 Issue 1.1 ...
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BOARD LAYOUT 6.1 THERMAL DISSIPATION Thermal dissipation of the STPC depends mainly on supply voltage result, when the system does not need to work at 3.3V, it may be to reduce the voltage to 3.15V for example. ...
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BOARD LAYOUT When considering thermal dissipation, the most important - and not the more obvious - part of the layout is the connection between the ground balls and the ground layer. A 1-wire connection is shown in Figure 6-2. The ...
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Figure 6-4. Optimum layout for central ground ball The PBGA Package also dissipates heat through peripheral ground balls. When a heat sink is placed on the device, heat is more uniformely spread throughout the moulding increasing heat dissipation through the ...
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BOARD LAYOUT Figure 6-6. Bottom side layout and decoupling A local ground plane on opposite side of the board as shown in Figure 6-6 improves thermal dissipa- tion used to connect decoupling capacitances but can also be used ...
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HIGH SPEED SIGNALS Some Interfaces of the STPC run at high speed and have to be carefully routed or even shielded. Here is the list of these interfaces, in decreasing speed order: - Memory Interface. - Graphics and video ...
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BOARD LAYOUT 52/55 Issue 1.1 ...
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ORDERING DATA 7.1 ORDERING CODES STMicroelectronics Prefix Product Family PC: PC Compatible Product ID I01: Industrial Core Speed 66: 66MHz 80: 80MHz Package BT: 388 Overmoulded BGA Temperature Range C: Commercial Tcase = 0 to +100 C I: Industrial ...
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... ORDERING DATA 7.2 AVAILABLE PART NUMBERS Core Frequency Part Number (MHz) STPCI0166BTC3 66 STPCI0180BTC3 80 STPCI0166BTI3 66 STPCI0180BTI3 80 54/55 Tcase Range CPU Mode ( +100 - +100 C DX Issue 1.1 Operating Voltage (V) 3.3V 0.3V ...
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. ...