MPC8572CLPXARLD FREESCALE [Freescale Semiconductor, Inc], MPC8572CLPXARLD Datasheet - Page 45
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MPC8572CLPXARLD
Manufacturer Part Number
MPC8572CLPXARLD
Description
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MPC8572CLPXARLD.pdf
(140 pages)
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Change in V
Output current on short to GND
Note:
1. This will not align to DC-coupled SGMII. XV
2. |V
3. The |V
4. V
Freescale Semiconductor
A & B) or XMITEQEF (for SerDes 2 lanes E & E) bit field of MPC8572E’s SerDes 2 Control Register:
•The MSbit (bit 0) of the above bit field is set to zero (selecting the full V
•The LSbits (bit [1:3]) of the above bit field is set based on the equalization setting shown in table.
OS
OD
•
is also referred to as output common mode voltage.
| = |V
OD
5.The |V
variation (V
SD2_TX[n].
MPC8572E SGMII
SerDes Interface
| value shown in the table assumes the following transmit equalization setting in the XMITEQAB (for SerDes 2 lanes
Parameter
OS
SD2_TXn
between “0” and “1”
OD
Transmitter
| value shown in the Typ column is based on the condition of XV
MPC8572E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 4
OS
- V
Table 37. SGMII DC Transmitter Electrical Characteristics (continued)
Figure 22. 4-Wire AC-Coupled SGMII Serial Link Connection Example
Receiver
=550mV), SerDes2 transmitter is terminated with 100-Ω differential load between SD2_TX[n] and
SD2_TXn
|. |V
50 Ω
50 Ω
50 Ω
50 Ω
OD
| is also referred as output differential peak voltage. V
Symbol
I
SA
Δ
SD2_TXn
SD2_RXn
SD2_TXn
SD2_RXn
V
, I
OS
SB
DD_SRDS2-Typ
C
C
Min
TX
TX
—
—
=1.1 V.
C
C
TX
TX
SD_RXm
SD_RXm
SD_TXm
SD_TXm
DD-DIFF-p-p
Typ
—
—
Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
50 Ω
50 Ω
50 Ω
50 Ω
DD_SRDS2-Typ
amplitude - power up default);
Receiver
Transmitter
TX-DIFFp-p
Max
25
40
=1.1V, no common mode offset
= 2*|V
Unit
mV
mA
OD
|
.
Notes
—
—
45
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