MPC859T FREESCALE [Freescale Semiconductor, Inc], MPC859T Datasheet - Page 23

• Manufacturer Part Number: MPC859T
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

1
2
3
4
5
6
7
8
9
MOTOROLA
Num
B37 UPWAIT valid to CLKOUT falling
B38 CLKOUT falling edge to UPWAIT
B39 AS valid to CLKOUT rising edge
B40 A(0:31), TSIZ(0:1), RD/WR, BURST,
B41 TS valid to CLKOUT rising edge (setup
B42 CLKOUT rising edge to TS valid (hold
B43 AS negation to memory controller
For part speeds above 50 MHz, use 9.80 ns for B11a.
The timing required for BR input is relevant when the MPC866/859 is selected to work with the internal bus arbiter.
The timing for BG input is relevant when the MPC866/859 is selected to work with the external bus arbiter.
For part speeds above 50 MHz, use 2 ns for B17.
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of CLKOUT, in which the TA input signal
is asserted.
For part speeds above 50 MHz, use 2 ns for B19.
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of CLKOUT. This timing is valid only for
read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats, where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to CLKOUT and synchronized internally. The timings specified in B37
and B38 are specified to enable the freeze of the UPM output signals as described in Figure 20.
The AS signal is considered asynchronous to CLKOUT. The timing B39 is specified in order to allow the behavior
specified in Figure 23.
edge
valid
= 0.00 x B1 + 7.00)
valid to CLKOUT rising edge (MIN =
0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 7.00)
time) (MIN = 0.00 x B1 + 2.00)
signals negation (MAX = TBD)
8
8
(MIN = 0.00 x B1 + 1.00)
(MIN = 0.00 x B1 + 6.00)
Characteristic
Freescale Semiconductor, Inc.
Table 9. Bus Operation Timings (continued)
For More Information On This Product,
MPC866/859 Hardware Specifications
9
(MIN
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6.00
1.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
—
—
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
40 MHz
TBD
Max
—
—
—
—
—
—
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
50 MHz
Max
TBD
—
—
—
—
—
—
Bus Signal Timing
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
66 MHz
TBD
Max
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
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