MPC870 FREESCALE [Freescale Semiconductor, Inc], MPC870 Datasheet - Page 23

• Manufacturer Part Number: MPC870
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Bus Signal Timing
23
1
2
3
4
5
6
7
8
9
For part speeds above 50 MHz, use 9.80 ns for B11a.
The timing required for BR input is relevant when the MPC875/870 is selected to work with the internal bus arbiter.
For part speeds above 50 MHz, use 2 ns for B17.
The D(0:31) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input signal is asserted.
For part speeds above 50 MHz, use 2 ns for B19.
The D(0:31) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read
The timing B30 refers to CS when ACS = 00 and to WE(0:3) when CSNT = 0.
The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in
The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior
Num
B42
B43
The timing for BG input is relevant when the MPC875/870 is selected to work with the external bus arbiter.
accesses controlled by chip-selects under control of the user-programmable machine (UPM) in the memory
controller, for data beats where DLT3 = 1 in the RAM words. (This is only the case where data is latched on the falling
edge of CLKOUT.)
B37 and B38 are specified to enable the freeze of the UPM output signals as described in
specified in
CLKOUT rising edge to TS valid (hold
time) (MIN = 0.00
AS negation to memory controller signals
negation (MAX = TBD)
Figure
22.
Characteristic
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
×
B1 + 2.00)
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Table 10. Bus Operation Timings (continued)
2.00
Min
—
33 MHz
Max
TBD
—
2.00
Min
—
40 MHz
TBD
Max
—
2.00
Min
—
66 MHz
TBD
Max
—
Figure
Freescale Semiconductor
2.00
Min
—
80 MHz
19.
Max
TBD
—
Unit
ns
ns