MPC870 FREESCALE [Freescale Semiconductor, Inc], MPC870 Datasheet - Page 3

no-image

MPC870

Manufacturer Part Number
MPC870
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC870CVR133
Manufacturer:
Freescale
Quantity:
560
Part Number:
MPC870CVR133
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC870CVR66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC870CZT133
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC870CZT133
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
MPC870CZT66
Manufacturer:
MOT
Quantity:
12 388
Part Number:
MPC870CZT66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC870CZT66
Quantity:
100
Company:
Part Number:
MPC870CZT66
Quantity:
20
Part Number:
MPC870VR133
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC870VR133
Manufacturer:
FREE
Quantity:
20 000
Part Number:
MPC870VR66
Manufacturer:
Freescale Semiconductor
Quantity:
135
Part Number:
MPC870VR80
Manufacturer:
Freescale
Quantity:
679
Freescale Semiconductor
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbyte–256 Mbyte)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers or two 32-bit timers
— Gate mode can enable/disable counting.
— Interrupt can be masked on reference match and event capture
Two fast Ethernet controllers (FEC)—Two 10/100 Mbps Ethernet/IEEE 802.3 CDMA/CS that
interface through MII and/or RMII interfaces
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Clock synthesizer
— Decrementer and time base
— Reset controller
— IEEE 1149.1 test access port (JTAG)
Security engine is optimized to handle all the algorithms associated with IPsec, SSL/TLS, SRTP,
802.11i, and iSCSI processing. Available on the MPC875, the security engine contains a
crypto-channel, a controller, and a set of crypto hardware accelerators (CHAs). The CHAs are:
— Data encryption standard execution unit (DEU)
— Advanced encryption standard unit (AESU)
— Message digest execution unit (MDEU)
— Master/slave logic, with DMA
— Crypto-channel supporting multi-command descriptors
Interrupts
— Six external interrupt request (IRQ) lines
– DES, 3DES
– Two key (K1, K2, K1) or three key (K1, K2, K3)
– ECB and CBC modes for both DES and 3DES
– Implements the Rinjdael symmetric key cipher
– ECB, CBC, and counter modes
– 128-, 192-, and 256-bit key lengths
– SHA with 160- or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
– 32-bit address/32-bit data
– Operation at 8xx bus frequency
Integrated controller managing crypto-execution units
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC875/MPC870 Hardware Specifications, Rev. 3.0
Features
3

Related parts for MPC870