DP83848J_07 NSC [National Semiconductor], DP83848J_07 Datasheet - Page 73
DP83848J_07
Manufacturer Part Number
DP83848J_07
Description
Manufacturer
NSC [National Semiconductor]
Datasheet
1.DP83848J_07.pdf
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8.2.21 100BASE-TX Signal Detect Timing
Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant.
8.2.22 100 Mb/s Internal Loopback Timing
Note: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time”
of up to 550 µs during which time no data will be present at the receive MII outputs. The 100BASE-TX timing specified is
based on device delays after the initial 550µs “dead-time”.
Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
T2.21.1
T2.21.2
T2.22.1
Parameter
Parameter
PMD Input Pair
SD+ internal
SD Internal Turn-on Time
SD Internal Turn-off Time
TX_EN to RX_DV Loopback
RXD[3:0]
TXD[3:0]
TX_CLK
RX_CLK
TX_EN
RX_DV
CRS
Description
Description
T2.21.1
100 Mb/s internal loopback mode
T2.22.1
73
Notes
Notes
T2.21.2
Min
Min
Typ
Typ
www.national.com
Max
Max
350
240
1
Units
Units
ms
µs
ns
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