MC68HC11F1CFN5 MOTOROLA [Motorola, Inc], MC68HC11F1CFN5 Datasheet
MC68HC11F1CFN5
Available stocks
Related parts for MC68HC11F1CFN5
MC68HC11F1CFN5 Summary of contents
Page 1
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary 8-Bit Microcontroller 1 Introduction The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units (MCUs). High-speed expanded systems required the development of this chip with its extra input/output (I/O) ports, an ...
Page 2
... C 3 MHz MHz – MHz MC Order Number MC68HC11F1PU5 MC68HC11F1CPU2 MC68HC11F1CPU3 MC68HC11F1CPU4 MC68HC11F1CPU5 MC68HC11F1VPU2 MC68HC11F1VPU3 MC68HC11F1VPU4 MC68HC11F1MPU2 MC68HC11F1MPU3 MC68HC11F1MPU4 MC68HC11F1FN5 MC68HC11F1CFN2 MC68HC11F1CFN3 MC68HC11F1CFN4 MC68HC11F1CFN5 MC68HC11F1VFN2 MC68HC11F1VFN3 MC68HC11F1VFN4 MC68HC11F1MFN2 MC68HC11F1MFN3 MC68HC11F1MFN4 MC Order Number MC68L11F1FN3 MC68L11F1CFN3 MC68L11F1PU3 MC68L11F1CPU3 MC68HC11F1/FC0 MC68HC11FTS/D ...
Page 3
Table 3 MC68HC11FC0 Standard Device Ordering Information Package 64-Pin Quad Flat Pack (QFP) 80-Pin Thin Quad Flat Pack (TQFP) Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information Package 64-Pin Quad Flat Pack (QFP) 80-Pin Thin Quad ...
Page 4
Section 1 Introduction 1.1 Features ......................................................................................................................................1 1.2 Ordering Information ...................................................................................................................2 1.3 Block Diagrams ..........................................................................................................................6 2 Pin Assignments and Signal Descriptions 2.1 MC68HC11F1 Pin Assignments ..................................................................................................8 2.2 MC68HC11FC0 Pin Assignments .............................................................................................10 2.3 Pin Descriptions ........................................................................................................................12 3 Control Registers 3.1 MC68HC11F1 Control ...
Page 5
Register ADCTL ................ A/D Control/Status .........................................................$1030 ..........................55 BAUD .................. Baud Rate......................................................................$102B ..........................44 BPROT................ Block Protect..................................................................$1035 ..........................29 CFORC ............... Timer Force Compare....................................................$100B ..........................59 CONFIG .............. EEPROM Mapping, COP, EEPROM Enables ...............$103F ............. 24 COPRST ............. Arm/Reset COP Timer Circuitry.....................................$103A ..........................27 CSCTL ...
Page 6
Block Diagrams POWER PAI/0C1 PA7 OC2/OC1 PA6 OC3/OC1 PA5 OC4/OC1 PA4 IC4/OC5/OC1 PA3 IC3 PA2 IC2 PA1 IC1 PA0 ADDRESS BUS PORT B Figure 1 MC68HC11F1 Block Diagram MOTOROLA 6 XTAL EXTAL IRQ XIRQ ...
Page 7
POWER PAI/0C1 PA7 OC2/OC1 PA6 OC3/OC1 PA5 OC4/OC1 PA4 IC4/OC5/OC1 PA3 IC3 PA2 IC2 PA1 IC1 PA0 PE6 PE5 PE4 PE3 PE2 PE1 ADDRESS BUS PORT B Figure 2 MC68HC11FC0 Block Diagram MC68HC11F1/FC0 MC68HC11FTS/D E ...
Page 8
Pin Assignments and Signal Descriptions 2.1 MC68HC11F1 Pin Assignments 10 PC1/DATA1 11 PC2/DATA2 12 PC3/DATA3 13 PC4/DATA4 14 PC5/DATA5 15 PC6/DATA6 PC7/DATA7 16 17 RESET 18 XIRQ 19 IRQ 20 PG7/CSPROG 21 PG6/CSGEN 22 PG5/CSIO1 23 PG4/CSIO2 24 PG3 ...
Page 9
PB6/ADDR14 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PF7/ADDR7 10 PF6/ADDR6 11 PF5/ADDR5 12 PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 17 PE0/AN0 18 PE4/AN4 ...
Page 10
MC68HC11FC0 Pin Assignments PB6/ADDR14 1 PB5/ADDR13 2 3 PB4/ADDR12 PB3/ADDR11 4 PB2/ADDR10 5 PB1/ADDR9 6 PB0/ADDR8 7 PF7/ADDR7 8 PF6/ADDR6 9 10 PF5/ADDR5 PF4/ADDR4 11 PF3/ADDR3 12 13 PF2/ADDR2 PF1/ADDR1 14 PF0/ADDR0 Figure 5 MC68HC11FC0 ...
Page 11
PB6/ADDR14 3 PB5/ADDR13 4 PB4/ADDR12 5 PB3/ADDR11 6 PB2/ADDR10 7 PB1/ADDR9 8 PB0/ADDR8 9 PF7/ADDR7 10 PF6/ADDR6 11 PF5/ADDR5 12 PF4/ADDR4 13 PF3/ADDR3 14 PF2/ADDR2 15 PF1/ADDR1 16 PF0/ADDR0 PE4 19 NC ...
Page 12
Pin Descriptions V and the positive power input to the MCU, and V DD RESET This active-low input initializes the MCU to a known startup state. It also acts as an open-drain output to ...
Page 13
Port Signals On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports and G) and one 6-bit port (port D). On the MC68HC11FC0, either pins are available, depending on the ...
Page 14
Control Registers The MC68HC11F1 and MC68HC11FC0 control registers determine most of the system’s operating characteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics are summarized in the following table. Addresses shown are the default locations ...
Page 15
Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued) Bit 7 6 $1022 OC1I OC2I OC3I $1023 OC1F OC2F OC3F $1024 TOI RTII PAOVI $1025 TOF RTIF PAOVF $1026 0 PAEN PAMOD $1027 Bit 7 6 $1028 SPIE SPE DWOM ...
Page 16
MC68HC11FC0 Control Registers Table 6 MC68HC11FC0 Register and Control Bit Assignments Bit 7 6 $1000 PA7 PA6 $1001 DDA7 DDA6 DDA5 $1002 PG7 PG6 PG5 $1003 DDG7 DDG6 DDG5 $1004 PB7 PB6 $1005 PF7 PF6 $1006 PC7 PC6 $1007 ...
Page 17
Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued) Bit 7 6 $1026 0 PAEN PAMOD $1027 Bit 7 6 $1028 SPIE SPE DWOM $1029 SPIF WCOL $102A Bit 7 6 $102B TCLR SCP2 SCP1 $102C R8 T8 $102D TIE ...
Page 18
Operating Modes and System Initialization The 16-bit address bus can access 64 Kbytes of memory. Because the MC68HC11F1 and MC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM and the address bus is non-multiplexed. ...
Page 19
Memory Maps $0000 — — $03FF — — EXTERNAL $1000 — — $105F — — EXTERNAL $BF00 — — $BFFF — — $FE00 — $FFC0 — — $FFFF — — SINGLE EXPANDED CHIP MODA = 0 MODA = 1 ...
Page 20
EXTERNAL $1000 — — $105F — — EXTERNAL $BF00 — — $BFFF — — $FE00 — $FFC0 — — $FFFF — — SINGLE EXPANDED CHIP MODA = 0 MODA = 1 MODB = 1 ...
Page 21
RBOOT — Read Bootstrap ROM RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT can only be written in special modes but can be read anytime Boot loader ROM disabled ...
Page 22
INIT — RAM and I/O Mapping (MC68HC11F1 only) Bit 7 6 RAM3 RAM2 RESET The INIT register can be written only once in first 64 cycles out of reset in normal modes any time in special ...
Page 23
CWOM — Port C Wired-OR Mode Option Refer to 7.8 Parallel I/O Registers, page 37. CLK4X — 4XCLK Output Enable This bit can only be written once after reset in all modes 4XOUT clock output is disabled 1 ...
Page 24
CONFIG — EEPROM Mapping, COP, EEPROM Enables Bit 7 6 EE3 EE2 RESET Unaffected by reset Bits 7:3 — See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.) NOCOP — COP ...
Page 25
Resets and Interrupts There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own reset vector: • RESET pin • Clock monitor failure • Computer operating properly (COP) failure There are 22 interrupt sources serviced ...
Page 26
Table 11 Interrupt and Reset Vector Assignments Vector Address FFC0 FFD4, D5 FFD6, D7 SCI Serial System SCI Transmit Complete SCI Transmit Data Register Empty SCI Idle Line Detect SCI Receiver Overrun SCI Receive Data Register Full FFD8, ...
Page 27
CR[1:0] — COP Timer Rate Select The COP system is driven by a constant frequency of E/2 tor to arrive at the COP time-out rate. Table 12 COP Watchdog Time-Out Periods Frequency Tolerance 1 MHz -0/+32.768 ms 2 MHz -0/+16.384 ...
Page 28
Table 13 Highest Priority Interrupt Selection (Continued) PSEL[3:0] 1011 1100 1101 1110 1111 CONFIG — EEPROM Mapping, COP, EEPROM Enables Bit 7 6 EE3 EE2 RESET U U Bits 7:3, 1:0 — See 6.2 EEPROM Registers, page 30. NOCOP — ...
Page 29
Electrically Erasable Programmable ROM The MC68HC11F1 has 512 bytes of electrically erasable programmable ROM (EEPROM). A nonvola- tile, EEPROM-based configuration register (CONFIG) controls whether the EEPROM is present or ab- sent and determines its position in the memory map. ...
Page 30
PPROG — EEPROM Programming Control Bit 7 6 ODD EVEN RESET 0 0 ODD — Program Odd Rows (TEST) EVEN — Program Even Rows (TEST) ROW and BYTE — Row Erase Select Bit and Byte Erase Select The value of ...
Page 31
Bit 1 — Not implemented. Reads always return one and writes have no effect. EEON — EEPROM Enable This bit is forced to one in single-chip and bootstrap modes. In test mode, EEON is forced to zero out of reset. ...
Page 32
STAB $FE00 LDAB #$07 STAB $103B JSR DLY10 CLR $103B 6.3.3 Row Erase The following example shows how to perform a fast erase of large sections of EEPROM. This example assumes that index register X contains the address of a ...
Page 33
Parallel Input/Output On the MC68HC11F1, either pins are available for general-purpose I/O, depending on the package. These pins are arranged into ports and G. On the MC68HC11FC0, either 52 or ...
Page 34
Port G Port eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register (DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expanded modes. When any ...
Page 35
DDRG — Port G Data Direction Register Bit 7 6 DDG7* DDG6 DDG5 RESET Following reset in expanded and test modes, PG7/CSPRG is configured as a program chip select, forcing the pin output pin, ...
Page 36
PORTD — Port D Data Register Bit RESET Alternate — — Function: DDRD — Port D Data Direction Register Bit RESET For DDRx bits input and ...
Page 37
CWOM — Port C Wired-OR Mode Option This bit affects all port C pins together Port C outputs are normal CMOS outputs 1 = Port C outputs act as open-drain outputs CLK4X — 4XCLK Output Enable Refer to ...
Page 38
Chip-Selects Chip selects eliminate the need for additional external components to interface with peripherals in ex- panded non-multiplexed modes. Chip-select registers control polarity, address block size, base ad- dress, and clock stretching. 8.1 Chip-Select Operation There are four programmable ...
Page 39
Table 16 Chip Select Clock Stretch Control CSCTL — Chip-Select Control Bit 7 6 IO1EN IO1PL IO2EN RESET PCSEN is set out of reset in expanded modes and cleared in single-chip modes. IO1EN — I/O Chip-Select 1 ...
Page 40
PCSEN — Program Chip-Select Enable Reset clears PCSEN in single-chip modes and sets PCSEN in expanded modes CSPROG disabled 1 = CSPROG enabled PSIZA, PSIZB — Select Size of Program Chip-Select Table 18 Program Chip Select Size Control ...
Page 41
Bit 5 — Not implemented. Reads always return zero and writes have no effect. GNPOL — General-Purpose Chip-Select Polarity 0 = CSGEN is active low 1 = CSGEN is active high GAVLD — General-Purpose Chip-Select Address Valid 0 = CSGEN ...
Page 42
Serial Communications Interface (SCI) The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is one of two independent serial I/O subsystems in the MC68HC11F1 and MC68HC11FC0. The SCI has a standard non-return to zero (NRZ) format (one ...
Page 43
RECEIVER BAUD RATE CLOCK DDD0 PD0 PIN BUFFER RxD AND CONTROL DISABLE DRIVER RE WAKEUP LOGIC SCCR1 SCI CONTROL 1 SCI Tx SCI INTERRUPT REQUESTS REQUEST Figure 10 SCI Receiver Block Diagram MC68HC11F1/FC0 MC68HC11FTS/D 16 DATA RECOVERY ...
Page 44
SCI Registers BAUD — Baud Rate Bit 7 6 TCLR SCP2 RESET TCLR — Clear Baud Rate Counters (TEST) Bit 6 — Not implemented. Reads always return zero and writes have no effect. RCKB — SCI Baud-Rate ...
Page 45
Figure 11 illustrates the SCI baud rate timing chain. The prescaler select bits determine the highest baud rate. The rate select bits determine additional divide-by-two stages to arrive at the receiver timing (RT) clock rate. The baud rate clock is ...
Page 46
SCCR1 — SCI Control Register 1 Bit RESET Unaffected by reset R8 — Receive Data Bit set, R8 stores the ninth bit of the receive data character. T8 ...
Page 47
RWU — Receiver Wake Up Control 0 = Normal SCI receiver 1 = Wake up enabled and receiver interrupt inhibited SBK — Send Break 0 = Break generator off 1 = Break codes generated as long as SBK = 1 ...
Page 48
Bit 0 — Not implemented. Reads always return zero and writes have no effect. SCDR — Serial Communications Data Register Bit 7 6 Bit 7 6 RESET Indeterminate value Reading SCDR retrieves the last byte received ...
Page 49
Serial Peripheral Interface The serial peripheral interface (SPI) allows the MCU to communicate synchronously with peripheral de- vices and other microprocessors. The SPI protocol facilitates rapid exchange of serial data between de- vices in a control system. The MC68HC11F1 ...
Page 50
SPI Registers SPCR — SPI Control Register Bit 7 6 SPIE SPE RESET Unaffected by reset SPIE — SPI Interrupt Enable When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the ...
Page 51
SPR[1:0] — SPI Clock Rate Selects These two bits select the SPI clock (SCK) rate when the device is configured as a master. When the device is configured as a slave, the bits have no effect. Refer to Table 23. ...
Page 52
OPT2 — System Configuration Option Register 2 Bit 7 6 GWOM CWOM RESET 0 0 Bits [7:4] — See 4.3 System Initialization Registers, page 22. Bits — Not implemented. Reads always return zero and writes have no ...
Page 53
Analog-to-Digital Converter The MC68HC11F1 analog-to-digital (A/D) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. The A/D system is an 8-channel, 8-bit, multiplexed- input, successive-approximation converter, accurate to 1 least significant bit (LSB). Because ...
Page 54
Input Pins Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during the sample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is ...
Page 55
A/D Registers ADCTL — A/D Control/Status Bit 7 6 CCF 0 RESET Indeterminate value CCF — Conversions Complete Flag A read-only status indicator, this bit is set when all four A/D result registers contain valid ...
Page 56
ADR1 – ADR4 — A/D Results $x031 Bit 7 6 $x032 Bit 7 6 $x033 Bit 7 6 $x034 Bit 7 6 Each read-only result register holds an eight-bit conversion result. Writes to these registers have no ef- fect. Data ...
Page 57
Main Timer The main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. The timer drives the three input capture (IC) channels, four output compare (OC) channels, one channel pro- grammable for either IC or ...
Page 58
PRESCALER E CLOCK Divide PR1 PR0 16-BIT TIMER BUS 16-BIT COMPARATOR = TOC1 (HI) TOC1 (LO) 16-BIT COMPARATOR = TOC2 (HI) TOC2 (LO) 16-BIT COMPARATOR = TOC3 (HI) TOC3 (LO) 16-BIT COMPARATOR = TOC4 ...
Page 59
Timer Registers CFORC — Timer Force Compare Bit 7 6 FOC1 FOC2 RESET FOCx — Force Output Compare x Action 0 = Not affected 1 = Output compare x action occurs, but OCxF flag bit is not ...
Page 60
TIC1–TIC3 — Timer Input Capture $x010 Bit 15 14 $x011 Bit 7 6 $x012 Bit 15 14 $x013 Bit 7 6 $x014 Bit 15 14 $x015 Bit 7 6 TICx registers are not affected by reset. TOC1–TOC4 — Timer Output ...
Page 61
OMx OLx TCTL2 — Timer Control 2 Bit 7 6 EDG4B EDG4A EDG1B RESET EDGxB, EDGxA — Input Capture Edge Control Each EDGxB, EDGxA pair determines the polarity of the ...
Page 62
OCxF — Output Compare x Flag Set each time the counter matches output compare x value. I4/O5F — Input Capture 4/Output Compare 5 Flag Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL. ICxF ...
Page 63
RTIF — Real-Time Interrupt Flag Set periodically at a rate based on bits RTR[1:0] in the PACTL register. Bits [5:4] — See 13.2 Pulse Accumulator Registers, page 65. Bits [3:0] — Not implemented. Reads always return zero and writes have ...
Page 64
Pulse Accumulator The pulse accumulator can be used either to count events or measure the duration of a particular event. In event counting mode, the pulse accumulator’s 8-bit counter increments each time a specified edge is detected on the ...
Page 65
Bits[7:6] — See 12.2 Timer Registers, page 62. PAOVI — Pulse Accumulator Overflow Interrupt Enable 0 = Pulse accumulator overflow interrupt disabled 1 = Interrupt requested when PAOVF in TFLG2 is set PAII — Pulse Accumulator Interrupt Enable 0 = ...
Page 66
Table 33 Pulse Accumulator Edge Control PAMOD PEDGE Bit 3 — Not implemented. Reads always return zero and writes have no effect. Bits [2:0] — See 12.2 Timer Registers, page 63. PACNT — Pulse Accumulator Count ...
Page 67
MC68HC11F1/FC0 MC68HC11FTS/D MOTOROLA 67 ...
Page 68
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...