PIC18F242 MICROCHIP [Microchip Technology], PIC18F242 Datasheet - Page 209

• Manufacturer Part Number: PIC18F242
• Description: 28/40-pin High Performance, Enhanced FLASH Microcontrollers with 10-Bit A/D
• Manufacturer: MICROCHIP [Microchip Technology]

19.4
The overall structure of the code protection on the
PIC18 FLASH devices differs significantly from other
PICmicro devices.
The user program memory is divided into five blocks.
One of these is a boot block of 512 bytes. The remain-
der of the memory is divided into four blocks on binary
boundaries.
FIGURE 19-3:
TABLE 19-3:
© 2006 Microchip Technology Inc.
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
Legend: Shaded cells are unimplemented.
File Name
Program Verification and
Code Protection
Unimplemented
Unimplemented
Unimplemented
(PIC18FX42)
16 Kbytes
Boot Block
Read 0’s
Read 0’s
Read 0’s
Block 0
Block 1
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
MEMORY SIZE/DEVICE
SUMMARY OF CODE PROTECTION REGISTERS
CODE PROTECTED PROGRAM MEMORY FOR PIC18F2XX/4XX
WRTD
Bit 7
CPD
—
—
—
—
Unimplemented
(PIC18FX52)
32 Kbytes
Boot Block
Read 0’s
Block 0
Block 1
Block 2
Block 3
EBTRB
WRTB
Bit 6
CPB
—
—
—
WRTC
Bit 5
—
—
—
—
—
000000h
0001FFh
000200h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
1FFFFFh
Address
Range
Each of the five blocks has three code protection bits
associated with them. They are:
• Code Protect bit (CPn)
• Write Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 19-3 shows the program memory organization
for 16- and 32-Kbyte devices, and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 19-3.
Bit 4
—
—
—
—
—
—
(Unimplemented Memory Space)
EBTR3
WRT3
Bit 3
CP3
—
—
—
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
EBTR2
WRT2
Bit 2
CP2
—
—
—
PIC18FXX2
EBTR1
WRT1
Bit 1
CP1
DS39564C-page 207
—
—
—
EBTR0
WRT0
Bit 0
CP0
—
—
—