AT83C26_07 ATMEL [ATMEL Corporation], AT83C26_07 Datasheet - Page 17
AT83C26_07
Manufacturer Part Number
AT83C26_07
Description
Multiple Smart Card Reader Interface With Power Management
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.AT83C26_07.pdf
(77 pages)
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Transparent mode arbitration system
7511D–SCR–02/07
The first between IO and CIO to force a low level becomes the master.
The slave signal is grounded after t1 delay:
The minimum delay for a pulse at 0 or 1 to be detected is between 0.5 and 1.5 CLK period
(depending on arrival time).
If IO and CIO are both grounded, CIO becomes the master.
The minimum delay to switch of master without electrical conflict is equal to:
If a master switch appears before this minimum delay, the electrical conflict delay is:
Figure 10. Bidirectional mode
Figure 11. Electrical conflict
CIO
t1 max = 2* (CLK period).
t2 min = 4 * (CLK period) + 2 * (DCCLK period) * (CLK period).
t2 = 2 * (DCCLK period) * (CLK period)
IO
CIO
IO
master
slave
t1
master
slave
t1
CIO pad becomes output
t2
t1
t2
master
slave
t1
master
slave
t1
AT83C26
17
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