AT83C5122_08 ATMEL [ATMEL Corporation], AT83C5122_08 Datasheet - Page 20

• Manufacturer Part Number: AT83C5122_08
• Description: C51 Microcontroller with USB and Smart Card Reader Interfaces
• Manufacturer: ATMEL [ATMEL Corporation]

Dual Data Pointer
Register (DDPTR)
20
AT83R5122, AT8xC5122/23
An access to external XRAM memory locations higher than the accessible size of the
memory (roll-over feature) will be performed with the MOVX DPTR instructions, with P0
and P2 as data/address busses, WR and RD as respectively write and read signals.
Accesses above XRAM size can only be done by the use of DPTR.
If EXTRAM=1 the MCU fetches the data from external XRAM Memory. There can be up
to 64 KBytes of external XRAM Memory.
The hardware configuration for external Data Memory Access is shown in Figure 9
Figure 9. Accessing to External XRAM Memory
MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri will
provide an eight-bit address multiplexed with data on Port 0 and any output port pins
can be used to output higher order address bits. This is to provide the external paging
capability. MOVX @DPTR will generate a sixteen-bit address. Port 2 outputs the high-
order eight address bits (DPH) while Port0 multiplexes the low-order eight address bits
(DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read or write sig-
nals on WR and RD.
Ports P0, P2 are not affected and RD, WR signals are not activated during access to
internal XRAM.
Note that external XRAM Memory access is only available on High Pin Count Packages.
External Program Memory and external XRAM Memory may be combined if desired by
applying the RD and PSEN signals to the inputs of an AND gate and using the ouput of
the gate as the read strobe to the external program/data memory.
The additional data pointer can be used to speed up code execution and reduce code
size.
The dual DPTR structure is a way by which the chip will specify the address of an exter-
nal data memory location. There are two 16-bit DPTR registers that address the external
memory, and a single bit called DPS = AUXR1.0 (see Table 7) that allow the program
code to switch between them (Figure 10).
AT83R5122,
WR#
ALE
RD#
P2
P0
PSEN
RD
AD7:0
A15:8
Latch
STROBE
A7:0
EXTERNAL XRAM
A15:8
A7:0
D7:0
OE
WR
MEMORY
4202F–SCR–07/2008