MC68HC711E20CFS2 MOTOROLA [Motorola, Inc], MC68HC711E20CFS2 Datasheet - Page 26

• Manufacturer Part Number: MC68HC711E20CFS2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

General Description
1.4.6 Non-Maskable Interrupt (XIRQ/V
1.4.7 MODA and MODB (MODA/LIR and MODB/V
Data Sheet
26
CAUTION:
NOTE:
The XIRQ input provides a means of requesting a non-maskable interrupt after
reset initialization. During reset, the X bit in the condition code register (CCR) is set
and any interrupt is masked until MCU software enables it. Because the XIRQ input
is level-sensitive, it can be connected to a multiple-source wired-OR network with
an external pullup resistor to V
interrupt.
Whenever XIRQ or IRQ is used with multiple interrupt sources each source must
drive the interrupt input with an open-drain type of driver to avoid contention
between outputs.
IRQ must be configured for level-sensitive operation if there is more than one
source of IRQ interrupt.
There should be a single pullup resistor near the MCU interrupt input pin (typically
4.7 kΩ). There must also be an interlock mechanism at each interrupt source so
that the source holds the interrupt line low until the MCU recognizes and
acknowledges the interrupt request. If one or more interrupt sources are still
pending after the MCU services a request, the interrupt line will still be held low and
the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is
cleared (normally upon return from an interrupt). Refer to
Interrupts.
V
EPROM/OTPROM programming. On devices without EPROM/OTPROM, this pin
is only an XIRQ input.
During EPROM programming of the MC68HC711E9 device, the V
may latch-up and be damaged if the input current is not limited to 10 mA. For more
information please refer to MC68HC711E9 8-Bit Microcontroller Unit Mask Set
Errata 3 (Motorola document order number 68HC711E9MSE3.
During reset, MODA and MODB select one of the four operating modes:
Refer to
After the operating mode has been selected, the load instruction register (LIR) pin
provides an open-drain output to indicate that execution of an instruction has
begun. A series of E-clock cycles occurs during execution of each instruction. The
LIR signal goes low during the first E-clock cycle of each instruction (opcode fetch).
This output is provided for assistance in program debugging.
PPE
•
•
•
•
is the input for the 12-volt nominal programming voltage required for
Single-chip mode
Expanded mode
Test mode
Bootstrap mode
Freescale Semiconductor, Inc.
Section 2. Operating Modes and On-Chip
For More Information On This Product,
Go to: www.freescale.com
PPE
General Description
)
STBY
DD
. XIRQ is often used as a power loss detect
)
Memory.
Section 5. Resets and
M68HC11E Family — Rev. 5
PPE
pin circuitry
MOTOROLA