ISL6209 INTERSIL [Intersil Corporation], ISL6209 Datasheet - Page 7
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ISL6209
Manufacturer Part Number
ISL6209
Description
High Voltage Synchronous Rectified Buck MOSFET Driver
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.ISL6209.pdf
(10 pages)
Available stocks
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Part Number
Manufacturer
Quantity
Price
Part Number:
ISL6209CB
Manufacturer:
INTERSIL
Quantity:
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Part Number:
ISL6209CBZ
Manufacturer:
INTERSIL
Quantity:
20 000
4
The equation governing the dead-time seen in Figure 5 is
expressed as:
The equation can be rewritten to solve for R
follows:
Internal Bootstrap Diode
This driver features an internal bootstrap Schottky diode.
Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit.
The bootstrap capacitor must have a maximum voltage
rating above the maximum battery voltage plus 5V. The
T
R
DELAY
1V
DELAY
FIGURE 5. ADDITIONAL PROGRAMMED DEAD-TIME
GATE A
50
45
40
35
30
25
20
15
10
5
0
0
=
=
[
(
------------------------------------------- -
(
T
160
160
DELAY
(t
DELAY
50
×
×
10
10
DELAY = VCC
–
t
–
PDHUGATE
) vs DELAY RESISTOR VALUE
–
15
6ns
15
100
)
×
)
R
FIGURE 4. PROGRAMMABLE DEAD-TIME: TOTAL DELAY = t
R
DELAY
DELAY
7
150
t
DELAY
]
(kΩ)
+
6ns
GATE B
200
DELAY
250
as
300
ISL6209
1V
bootstrap capacitor can be chosen from the following
equation:
where Q
charge the gate of the upper MOSFET. The ∆V
defined as the allowable droop in the rail of the upper drive.
As an example, suppose an upper MOSFET has a gate
charge, Q
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.22µF. A
good quality ceramic capacitor is recommended.
C
GATE A
BOOT
FIGURE 6. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
≥
GATE
20nC
----------------------- -
∆V
GATE
Q
GATE
BOOT
DELAY = RESISTOR TO GROUND
VOLTAGE
is the amount of gate charge required to fully
, of 25nC at 5V and also assume the droop in
PDHUGATE
50nC
t
Q
delay
GATE
= 5n - 50ns
+ t
= 100nC
delay
∆V
BOOT
(V)
BOOT
GATE B
term is