MC68HC912B32MFU8 MOTOROLA [Motorola, Inc], MC68HC912B32MFU8 Datasheet
MC68HC912B32MFU8
Related parts for MC68HC912B32MFU8
MC68HC912B32MFU8 Summary of contents
Page 1
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Technical Summary 16-Bit Microcontroller 1 Introduction The MC68HC912B32 microcontroller unit (MCU 16-bit device composed of standard on-chip pe- ripherals including a 16-bit central processing unit (CPU12), 32-Kbyte flash EEPROM, 1-Kbyte RAM, 768-byte EEPROM, an ...
Page 2
... Table 1 MC68HC912B32 Device Ordering Information Order Number Range MC68HC912B32FU8 MC68HC912B32CFU8 MC68HC912B32VFU8 40 to 105 C MC68HC912B32MFU8 40 to 125 C MC68C912B32FU8 MC68C912B32CFU8 MC68B912B32FU8 NOTE: This part is also available in 2-piece sample packs and 250-piece bricks. Evaluation boards, assemblers, compilers, and debuggers are available from Motorola and from third- party suppliers ...
Page 3
Section 1 Introduction 1.1 Features ......................................................................................................................................1 1.2 Ordering Information ...................................................................................................................2 1.3 MC68HC912B32 Block Diagram .................................................................................................5 2 Central Processing Unit 2.1 Programming Model ....................................................................................................................6 2.2 Data Types ..................................................................................................................................7 2.3 Addressing Modes .......................................................................................................................7 2.4 Indexed Addressing Modes .........................................................................................................8 2.5 Opcodes and Operands ...
Page 4
TABLE OF CONTENTS (Continued) Section 11 Pulse-Width Modulator 11.1 PWM Register Description ........................................................................................................65 11.2 PWM Boundary Cases ..............................................................................................................72 12 Standard Timer Module 12.1 Timer Registers .........................................................................................................................74 12.2 Timer Operation in Modes .........................................................................................................82 13 Serial Interface 13.1 Block Diagram ...........................................................................................................................83 13.2 ...
Page 5
MC68HC912B32 Block Diagram 32-KBYTE FLASH EEPROM V FP 1-KBYTE RAM 768-BYTE EEPROM CPU12 PERIODIC INTERRUPT BKGD SMODN / TAGHI SINGLE-WIRE BACKGROUND DEBUG MODULE EXTAL XTAL RESET PE0 XIRQ PE1 IRQ/V PP PE2 R/W PE3 LSTRB / TAGLO PE4 ECLK ...
Page 6
Central Processing Unit The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal reg- isters ( bits) for high-speed extended math instructions. The instruction set is a proper superset of ...
Page 7
Data Types The CPU12 supports the following data types: • Bit data • 8-bit and 16-bit signed and unsigned integers • 16-bit unsigned fractions • 16-bit addresses A byte is eight bits wide and can be accessed at any ...
Page 8
Indexed Addressing Modes The CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The ...
Page 9
Pinout and Signal Descriptions 3.1 MC68HC912B32 Pin Assignments The MC68HC912B32 is available in a 80-pin quad flat pack (QFP). Most pins perform two or more func- tions, as described in the 3.3 Signal Descriptions. Figure 3 shows pin assignments. ...
Page 10
Power Supply Pins MC68HC912B32 power and ground pins are described below and summarized in Table 4. 3.2.1 Internal Power (V ) and Ground (V DD Power is supplied to the MCU through V duration current demands on the power ...
Page 11
Signal Descriptions 3.3.1 Crystal Driver and External Clock Input (XTAL, EXTAL) These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. Out of reset the frequency applied to ...
Page 12
Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known start- up state. It also acts as an open-drain output to indicate that an internal failure has been detected ...
Page 13
External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share function with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for ...
Page 14
Table 5 MC68HC912B32 Signal Description Summary Pin Name Pin Number PW[3:0] 3–6 ADDR[7:0] 25–18 DATA[7:0] ADDR[15:8] 46–39 DATA[15:8] IOC[7:0] 16–12, 9–7 PAI 16 AN[7:0] 58–51 DBE 26 MODB, MODA 27, 28 IPIPE1, IPIPE0 27, 28 ECLK 29 RESET 32 EXTAL ...
Page 15
Port Signals The MC68HC912B32 incorporates eight ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In ad- dition to the pins described ...
Page 16
When the PUPE bit in the PUCR register is set, PE[7,3,2,0] are pulled up. PE[7,3,2,0] are pulled up ac- tive devices, while PE1 is always pulled up by means of an internal resistor. Neither port E nor DDRE is in ...
Page 17
Register DDRT determines pin direction of port T when used for general-purpose I/O. When DDRT bits are set, the corresponding pin is configured for output. On reset the DDRT bits are cleared and the cor- responding pin is configured for ...
Page 18
Table 6 MC68HC912B32 Port Description Summary Pin Data Direction Port Name Numbers DD Register (Address) Port A 46–39 PA[7:0] DDRA ($0002) Port B 25–18 DDRB ($0003) PB[7:0] Port AD 58–51 PAD[7:0] Port DLC 70–76 PDLC[6:0] DDRDLC ($00FF) PE[1:0] In Port ...
Page 19
Port Pull-Up, Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight ...
Page 20
Register Block The register block can be mapped to any 2-Kbyte boundary within the standard 64-Kbyte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block’s 16-bit address. The ...
Page 21
Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $0023 Bit 7 6 $0024 Bit 15 14 $0025 Bit 7 6 $0026– $003F $0040 CON23 CON01 PCKA2 $0041 PCLK3 PCLK2 PCLK1 $0042 0 0 ...
Page 22
Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $006F PAD7 PAD6 PAD5 $0070 Bit 7 6 $0071 0 0 $0072 Bit 7 6 $0073 0 0 $0074 Bit 7 6 $0075 0 0 $0076 Bit ...
Page 23
Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $0099 Bit 7 6 $009A Bit 15 14 $009B Bit 7 6 $009C Bit 15 14 $009D Bit 7 6 $009E Bit 15 14 $009F Bit 7 ...
Page 24
Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $00F2 EEODD EEVEN MARG $00F3 BULKP 0 $00F4 0 0 $00F5 0 0 $00F6 FSTE GADR $00F7 0 0 $00F8 IMSG CLKS $00F9 0 0 $00FA ALOOP ...
Page 25
Operating Modes and Resource Mapping Eight possible operating modes determine the operating configuration of the MC68HC912B32. Each mode has an associated default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses ...
Page 26
Normal Single-Chip Mode — There are no external address and data buses in this mode. All pins of ports A, B and E are configured as general-purpose I/O pins. Port E bits 1 and 0 are input-only with internal pull-ups ...
Page 27
MODE — Mode Register Bit 7 6 SMODN MODB MODA RESET RESET RESET RESET RESET RESET RESET MODE controls the MCU operating mode and various configuration ...
Page 28
EME — Emulate Port E Removing the registers from the map allows the user to emulate the function of these registers exter- nally. In single-chip mode PORTE and DDRE are always in the map regardless of the state of this ...
Page 29
MMSWAI — Memory Mapping Interface Stop in Wait Control This bit controls access to the memory mapping interface when in Wait mode Memory mapping interface continues to function during Wait mode Memory mapping interface access is ...
Page 30
The 32-Kbyte Flash EEPROM can be mapped to either the upper or lower half of the 64-Kbyte address space. When mapping conflicts occur, registers, RAM and EEPROM have priority over Flash EEPROM. To use memory expansion the part must be ...
Page 31
ROMON — Enable Flash EEPROM In expanded modes ROMON is reset to zero. In single-chip modes it is reset to one. If the internal RAM, registers, EEPROM, or BDM ROM (if active) are mapped to the same space as the ...
Page 32
Bus Control and Input/Output Internally the MC68HC912B32 has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or sixteen bits. There are cases where 8-bit and 16-bit accesses can ...
Page 33
PORTA — Port A Register Bit 7 6 Single PA7 PA6 Chip RESET: – – Exp Wide ADDR15 ADDR14 ADDR13 & Periph: DATA15 DATA14 DATA13 Expanded ADDR15 ADDR14 ADDR13 Narrow DATA15/7 DATA14/6 DATA13/5 Bits PA[7:0] are associated with addresses ADDR[15:8] ...
Page 34
PORTE — Port E Register Bit 7 6 Single Chip PE7 PE6 RESET: – – Alt. Pin MODB or DBE Function IPIPE1 This register is associated with external bus control signals and interrupt inputs including data bus en- able (DBE), ...
Page 35
In special single-chip mode, the E clock is enabled as a timing reference and the other bits of port E are configured for general-purpose I/O. In normal expanded modes, the reset vector is located in external memory. The E clock ...
Page 36
PUCR — Pull-Up Control Register Bit RESET These bits select pull-up resistors for any pin in the corresponding port that is currently configured as an input. This register is not in the map in ...
Page 37
Flash EEPROM The 32-Kbyte Flash EEPROM module for the MC68HC912B32 serves as electrically erasable and pro- grammable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently ...
Page 38
FEEMCR — Flash EEPROM Module Configuration Register Bit RESET This register controls the operation of the Flash EEPROM array. BOOTP cannot be changed when the LOCK control bit in the FEELCK register is set ...
Page 39
STRE — Spare Test Row Enable The spare test row consists of one Flash EEPROM array row. The reserved word at location 31 contains production test information which must be maintained through several erase cycles. When STRE is set, the ...
Page 40
ENPE — Enable Programming/Erase 0 = Disables program/erase voltage to Flash EEPROM 1 = Applies program/erase voltage to Flash EEPROM ENPE can be asserted only after LAT has been asserted and a write to the data and address latches has ...
Page 41
This method requires stopping the program/erase sequence at pe- riods for erasing) to determine if the Flash EEPROM is programmed/erased. After PPULSE EPULSE the location reaches the proper value, it must continue ...
Page 42
Programming the Flash EEPROM Programming the Flash EEPROM is accomplished by the following sequence. The V must be at the proper level prior to executing step 4 the first time. 1. Apply program/erase voltage to the V 2. Clear ...
Page 43
GET NEXT ADDRESS/DATA MC68HC912B32 MC68HC912B32TS/D START PROG TURN CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (n PP CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (t ) PPULSE CLEAR ...
Page 44
Erasing the Flash EEPROM The following sequence demonstrates the recommended procedure for erasing the Flash EEPROM. The V pin voltage must be at the proper level prior to executing step 4 the first time Turn on V ...
Page 45
CLEAR ERASE PULSE COUNTER (n NO MC68HC912B32 MC68HC912B32TS/D START ERASE TURN CLEAR MARGIN FLAG ) EP SET ERAS SET LAT WRITE TO ARRAY SET ENPE DELAY FOR DURATION OF ERASE PULSE (t ) EPULSE CLEAR ENPE DELAY ...
Page 46
Program/Erase Protection Interlocks The Flash EEPROM program and erase mechanisms provide maximum protection from accidental pro- gramming or erasure. The voltage required to program/erase the Flash EEPROM (V is not present, no programming/erasing will occur. Furthermore, the program/erase voltage ...
Page 47
EEPROM The MC68HC912B32 EEPROM serves as a 768-byte nonvolatile memory which can be used for fre- quently accessed static data or as fast access program code. The MC68HC912B32 EEPROM is arranged in a 16-bit configuration. The EEPROM array may ...
Page 48
BPROT4 (256 BYTES) $_E00 BPROT3 (256 BYTES) $_F00 BPROT2 (128 BYTES) $_F80 BPROT1 $_FC0 BPROT0 Figure 9 EEPROM Block Protect Mapping 8.2 EEPROM Control Registers EEMCR — EEPROM Module Configuration Bit RESET EESWAI ...
Page 49
BPROT[4:0] — EEPROM Block Protection 0 = Associated EEPROM block can be programmed and erased Associated EEPROM block is protected from being programmed and erased. Cannot be modified while programming is taking place (EEPGM = 1). Table 15 ...
Page 50
EEPROG — EEPROM Control Bit 7 6 BULKP 0 RESET BULKP — Bulk Erase Protection 0 = EEPROM can be bulk erased EEPROM is protected from being bulk or row erased. Read anytime. Write anytime if ...
Page 51
A program or erase operation should follow the sequence below: 1. Write BYTE, ROW and ERASE to the desired value; write EELAT = 1 2. Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = ...
Page 52
Resets and Interrupts CPU12 exceptions include resets and interrupts. Each exception has an associated 16-bit vector, which points to the memory location where the routine that handles the exception is located. Vectors are stored in the upper 128 bytes ...
Page 53
Vector Address Interrupt Source $FFE8, $FFE9 Timer channel 3 $FFE6, $FFE7 Timer channel 4 $FFE4, $FFE5 Timer channel 5 $FFE2, $FFE3 Timer channel 6 $FFE0, $FFE1 Timer channel 7 $FFDE, $FFDF Timer overflow $FFDC, $FFDD Pulse accumulator overflow $FFDA, $FFDB ...
Page 54
HPRIO — Highest Priority I Interrupt Bit RESET Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime. To give a maskable interrupt source highest priority, write the low byte of ...
Page 55
Clock and Watchdog Control Logic The COP watchdog system is enabled, with the CR[2:0] bits set for the shortest duration time-out. The clock monitor is disabled. The RTIF flag is cleared and automatic hardware interrupts are masked. The rate ...
Page 56
After the CCR is stacked, the I bit (and the X bit XIRQ interrupt service request is pending) is set to prevent other interrupts from disrupting the interrupt service routine. The interrupt vector for the high- est priority ...
Page 57
Clock Functions Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic ...
Page 58
Supply 5V 3V 10.5 Clock Function Registers All register addresses shown reflect the reset state. Registers may be mapped to any 2-Kbyte space. RTICTL — Real-Time Interrupt Control Register Bit 7 6 RTIE RSWAI RESET RTIE — Real-Time ...
Page 59
RTIFLG — Real-Time Interrupt Flag Register Bit 7 6 RTIF 0 RESET RTIF — Real-Time Interrupt Flag This bit is cleared automatically by a write to this register with this bit set Time-out has not yet ...
Page 60
Table 21 COP Watchdog Rates (RTBYP = 0) CR2 CR1 CR0 COPRST — Arm/Reset COP Timer ...
Page 61
REGISTER: BCR1 BITS: R1, R0 SC0BD MODULUS DIVIDER ..., 8190, 8191 SCI0 RECEIVE BAUD RATE ((16x SCI0 TRANSMIT BAUD RATE (1x) Figure 12 Clock Chain for SCI, BDLC, RTI, COP MC68HC912B32 MC68HC912B32TS/D ...
Page 62
PCLK REGISTER: TMSK2 TEN BITS: PR2, PR1, PR0 0:0:0 2 0:0:1 2 0:1:0 2 0:1:1 2 1:0:0 2 1:0:1 2 GATE LOGIC PORT T7 PAEN PCLK 5-BIT MODULUS COUNTER (PR0-PR4) REGISTER: SP0BR 2 BITS: SPR2, SPR1, SPR0 0:0:0 2 0:0:1 ...
Page 63
Pulse-Width Modulator The pulse-width modulator (PWM) subsystem provides four independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a combination of one 16-bit and two 8-bit PWM waveforms. Each waveform channel has a programmable period and a programmable ...
Page 64
CLOCK SOURCE (PCLK) PWCNTx GATE (CLOCK EDGE SYNC) PWENx PPOL = 0 PPOL = 1 PWDTY Figure 16 Block Diagram of PWM Center-Aligned Output Channel MOTOROLA 64 CENTR = 1 RESET DATA REGISTER (DUTY CYCLE) 8-BIT COMPARE = PWDTYx T ...
Page 65
PSBCK PSBCK IS BIT 0 OF PWCTL REGISTER. INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE. LIMBDM PCLK 0:0:0 0:0:0 2 0:0:1 0:0:1 0:1:0 2 0:1:0 0:1:1 0:1:1 2 1:0:0 1:0:0 2 1:0:1 1:0:1 2 ...
Page 66
CON01 — Concatenate PWM Channels 0 and 1 When concatenated, channel 0 becomes the high-order byte and channel 1 becomes the low-order byte. Channel 0 output pin is used as the output for this 16-bit PWM (bit 0 of port ...
Page 67
PPOL3 — PWM Channel 3 Polarity 0 = Channel 3 output is low at the beginning of the clock cycle; high when the duty count is reached Channel 3 output is high at the beginning of the clock ...
Page 68
PWPRES — PWM Prescale Counter Bit Bit 6 RESET PWPRES is a free-running 7-bit counter. Read anytime. Write only in special mode (SMOD = 1). PWSCAL0 — PWM Scale Register 0 Bit 7 6 Bit ...
Page 69
PWCNTx — PWM Channel Counters Bit 7 6 PWCNT0 Bit 7 6 PWCNT1 Bit 7 6 PWCNT2 Bit 7 6 PWCNT3 Bit 7 6 RESET Read and write anytime. A write will cause the PWM counter to reset ...
Page 70
PWDTYx — PWM Channel Duty Registers Bit 7 6 PWDTY0 Bit 7 6 PWDTY1 Bit 7 6 PWDTY2 Bit 7 6 PWDTY3 Bit 7 6 RESET Read and write anytime. The value in each duty register determines the ...
Page 71
PSBCK — PWM Stops while in Background Mode 0 = Allows PWM to continue while in background mode Disable PWM input clock when the part is in background mode. PWTST — PWM Special Mode Register (“Test”) Bit 7 ...
Page 72
PWM Boundary Cases The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: PWDTYx PWPERx PWPERx MOTOROLA 72 Table 23 PWM Boundary Conditions PWPERx PPOLx $FF $00 1 $FF $00 0 ...
Page 73
Standard Timer Module The standard timer module consists of a 16-bit software-programmable counter driven by a prescaler. It contains eight complete 16-bit input capture/output compare channels and one 16-bit pulse accumu- lator. This timer can be used for many ...
Page 74
Timer Registers Input/output pins default to general-purpose I/O lines until an internal function which uses that pin is specifically enabled. The timer overrides the state of the DDR to force the I/O state of each associated port line when ...
Page 75
When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit. TCNT — Timer Count Register Bit 7 ...
Page 76
TCTL1 — Timer Control Register 1 Bit 7 6 OM7 OL7 RESET TCTL2 — Timer Control Register 2 Bit 7 6 OM3 OL3 RESET Read or write anytime. OMn — Output Mode OLn — Output Level ...
Page 77
TMSK1 — Timer Interrupt Mask 1 Bit 7 6 C7I C6I RESET The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1 status register. If cleared, the cor- responding flag is disabled from causing a hardware ...
Page 78
The newly selected prescale factor will not take effect until the next synchronized edge where all pres- cale counter stages equal zero. TFLG1 — Timer Interrupt Flag 1 Bit 7 6 C7F C6F RESET TFLG1 indicates when interrupt ...
Page 79
TC3 — Timer Input Capture/Output Compare Register 3 Bit 7 6 Bit 15 14 Bit 7 6 TC4 — Timer Input Capture/Output Compare Register 4 Bit 7 6 Bit 15 14 Bit 7 6 TC5 — Timer Input Capture/Output Compare ...
Page 80
PEDGE — Pulse Accumulator Edge Control For PAMOD = 0 (event counter mode Falling edges on the pulse accumulator input pin (PT7/PAI) cause the count to be incremented 1 = Rising edges on the pulse accumulator input pin ...
Page 81
PACNT — 16-Bit Pulse Accumulator Count Register Bit 7 6 Bit 15 14 Bit 7 6 RESET Full count register access should take place in one clock cycle. A separate read/write for high byte and low byte will ...
Page 82
DDRT — Data Direction Register for Timer Port Bit 7 6 DDT7 DDT6 RESET Read or write anytime Configures the corresponding I/O pin for input only 1 = Configures the corresponding I/O pin for output The ...
Page 83
Serial Interface The serial interface of the MC68HC912B32 consists of two independent serial I/O sub-systems: the se- rial communication interface (SCI) and the serial peripheral interface (SPI). Each serial pin shares func- tion with the general-purpose port pins of ...
Page 84
MCLK BAUD RATE CLOCK DIVIDER SC0BD/SELECT DATA BUS TO PARITY INTERNAL DETECT LOGIC SC0CR1/SCI CTL 1 Figure 20 Serial Communications Interface Block Diagram 13.2.1 Data Format The serial data format requires the following conditions: • An idle-line in the high ...
Page 85
SCI Baud Rate Generation The basis of the SCI baud rate generator is a 13-bit modulus counter. This counter gives the generator the flexibility necessary to achieve a reasonable level of independence from the CPU operating frequen- cy and ...
Page 86
BTST — Baud Register Test Reserved for test function BSPL — Baud Rate Counter Split Reserved for test function BRLD — Baud Rate Reload Reserved for test function SC0CR1 — SCI Control Register 1 Bit 7 6 LOOPS WOMS RESET: ...
Page 87
WAKE — Wakeup by Address Mark/Idle 0 = Wake up by IDLE line recognition 1 = Wake up by address mark (last data bit set) ILT — Idle Line Type Determines which of two types of idle line detection will ...
Page 88
RWU — Receiver Wake-Up Control 0 = Normal SCI Receiver 1 = Enables the wake-up function and inhibits further receiver interrupts. Normally hardware wakes the receiver by automatically clearing this bit. SBK — Send Break 0 = Break generator off ...
Page 89
NF — Noise Error Flag Set during the same cycle as the RDRF bit but not set in the case of an overrun (OR Unanimous decision 1 = Noise on a valid start bit, any of the data ...
Page 90
R7/T7–R0/T0 — Receive/Transmit Data Bits Reads access the eight bits of the read-only SCI receive data register (RDR). Writes access the eight bits of the write-only SCI transmit data register (TDR). SC0DRL:SC0DRH form the 9-bit data word ...
Page 91
MCU P CLOCK (SAME AS E RATE) DIVIDER 128 256 SELECT SP0BR SPI BAUD RATE REGISTER SPI CONTROL SP0SR SPI STATUS REGISTER SPI INTERRUPT REQUEST Figure 21 Serial Peripheral Interface Block Diagram A clock ...
Page 92
Transfer SCK (CPOL=0) SCK (CPOL=1) SAMPLE I (MOSI/MISO) CHANGE O (MOSI pin) CHANGE O (MISO pin) SEL SS (O) (Master only) SEL SS ( MSB first (LSBF=0) : MSB LSB first (LSBF=1) : LSB Figure 22 SPI Clock ...
Page 93
SS Output Available in master mode only, SS output is enabled with the SSOE bit in the SP0CR1 register if the corresponding DDRS bit is set. The SS output pin will be connected to the SS input pin of ...
Page 94
Read or write anytime. SPIE — SPI Interrupt Enable 1 = Hardware interrupt sequence is requested each time the SPIF or MODF status flag is set 0 = SPI interrupts are inhibited SPE — SPI System Enable 0 = SPI ...
Page 95
Pin Mode SPC0 #1 Normal Bidirectional 1 #4 NOTES: 1. The serial pin control 0 bit enables bidirectional configurations. 2. Slave output is enabled if DDS4 = and MSTR = 0. (#1, #3) ...
Page 96
SP0DR register write collision 1 = Indicates that a serial transfer was in progress when the MCU tried to write new data into the SP0DR data register. MODF — SPI Mode Error ...
Page 97
DDS0 — Data Direction for Port S Bit 2 and Bit 0 If the SCI receiver is configured for two-wire SCI operation, corresponding port S pins will be input re- gardless of the state of these bits. DDS1 — Data ...
Page 98
Byte Data Link Communications Module (BDLC) The byte data link communications module (BDLC) provides access to an external serial communica- tion multiplex bus, operating according to the SAE J1850 protocol. 14.1 Features Features of the BDLC module include the ...
Page 99
Loopback Modes Two loopback modes are used to determine the source of bus faults. Digital Loopback is used to determine if a bus fault has been caused by failure in the node’s internal circuits or elsewhere in the network, ...
Page 100
Table 32 BDLC Rate Selection for Binary Frequencies MCU Clock Frequency ( 1.048576 MHz 2.09715 MHz 4.19430 MHz 8.38861 MHz Table 33 BDLC Rate Selection for Integer Frequencies MCU Clock Frequency ( 1.00000 MHz 2.00000 MHz 4.00000 MHz 8.00000 MHz ...
Page 101
RX4XE — Receive 4X Enable Reception of a BREAK symbol automatically clears this bit and sets the BSVR register to $1C BDLC transmits and receives at 10.4 kbps 1 = BDLC receive only operation NBFS ...
Page 102
TYPE 0 — NO IFR HEADER DATA FIELD TYPE 1 — SINGLE BYTE FROM A SINGLE RESPONDER HEADER DATA FIELD TYPE 2 — SINGLE BYTE FROM MULTIPLE RESPONDERS HEADER DATA FIELD TYPE 3 — MULTIPLE BYTES FROM A SINGLE RESPONDER ...
Page 103
BSVR — BDLC State Vector Register Bit RESET Decreases the CPU overhead associated with servicing interrupts while operating a serial communica- tion protocol. It provides an index offset that is directly related to the ...
Page 104
BDR — BDLC Data Register Bit RESET: – – Used to pass data to be transmitted to the J1850 bus from the CPU to the BDLC also used to pass data to the CPU. ...
Page 105
Table 36 Offset Bit Values and Transceiver Delay BARD Offset Bits (BO3, BO2, BO1, BO0) DLCSCR — Port DLC Control Register Bit RESET The BDLC port DLC functions as a general-purpose I/O port. BDLC ...
Page 106
DDRDLC — Port DLC Data Direction Register Bit DDDLC6 DDDLC5 RESET Read and write anytime. DDDLC[6:0] — Data Direction Port DLC Pin 6 through Pin Configure I/O pin for input only 1 ...
Page 107
If a BREAK symbol is received while the BDLC is transmitting or receiving, an invalid symbol interrupt will be generated. Reading the BSVR register will clear this interrupt condition. The BDLC will wait for the bus to idle, then wait ...
Page 108
Analog-To-Digital Converter The ATD is an 8-channel, 8-bit, multiplexed-input successive-approximation analog-to-digital converter, accurate to 1 least significant bit (LSB). It does not require external sample and hold circuits because of the type of charge redistribution technique used. The ATD ...
Page 109
ATDCTL1 — Reserved Bit RESET ATDCTL2 — ATD Control Register 2 Bit 7 6 ADPU AFFC ASWAI RESET The ATD control register 2 and 3 are used to select the power up ...
Page 110
Table 38 ATD Response to Background Debug Enable FRZ1 FRZ0 ATDCTL4 — ATD Control Register 4 Bit SMP1 RESET The ATD control register 4 is used to ...
Page 111
Prescale Value Total Divisor 00000 00001 00010 00011 00100 00101 00110 00111 01xxx 1xxxx NOTES: 1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become maximum conversion rate that can be used on this ATD module. ...
Page 112
Table 41 Multichannel Mode Result Register Assignment S8CM Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels make ...
Page 113
ATDSTAT — ATD Status Register Bit 7 6 SCF 0 RESET ATDSTAT — ATD Status Register Bit 7 6 CCF7 CCF6 RESET The ATD status registers contain the flags indicating the completion of ATD conversions. Normally, ...
Page 114
RST — Module Reset Bit When set, this bit causes all registers and activity in the module to assume the same state as out of power-on reset (except for ADPU bit in ATDCTL2, which remains set, allowing the ATD module ...
Page 115
Development Support Development support involves complex interactions between MC68HC912B32 resources and external development systems. The following section concerns instruction queue and queue tracking signals, background debug mode, and instruction tagging. 16.1 Instruction Queue The CPU12 instruction queue provides at ...
Page 116
CPU when necessary. Other BDM commands are firmware based, and require the CPU active background mode for execution. While BDM is active, the CPU executes a firmware program located in ...
Page 117
E CLOCK (TARGET MCU) HOST TRANSMIT 1 HOST TRANSMIT 0 PERCEIVED START OF BIT TIME SYNCHRONIZATION UNCERTAINTY Figure 27 BDM Host to Target Serial Bit Timing E CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU SPEEDUP PULSE HIGH-IMPEDANCE ...
Page 118
E CLOCK (TARGET MCU) HOST DRIVE TO BKGD PIN TARGET MCU DRIVE AND SPEEDUP PULSE PERCEIVED START OF BIT TIME BKGD PIN Figure 29 BDM Target to Host Serial Bit Timing (Logic 0) Figure 29 shows the host receiving a ...
Page 119
Table 43 BDM Commands Implemented in Hardware Command Opcode (Hex) BACKGROUND 90 READ_BD_BYTE E4 1 STATUS E4 READ_BD_WORD EC READ_BYTE E0 READ_WORD E8 WRITE_BD_BYTE C4 2 ENABLE_ FIRMWARE C4 WRITE_BD_WORD CC WRITE_BYTE C0 WRITE_WORD C8 NOTES: 1. STATUS command is ...
Page 120
Command Opcode (Hex) READ_NEXT 62 READ_PC 63 READ_D 64 READ_X 65 READ_Y 66 READ_SP 67 WRITE_NEXT 42 WRITE_PC 43 WRITE_D 44 WRITE_X 45 WRITE_Y 46 WRITE_SP TRACE1 10 TAGGO 18 16.2.4 BDM Registers Seven BDM registers are ...
Page 121
W/B — Word/Byte Transfer Flag 0 = Byte transfer 1 = Word transfer BD/U — BDM Map/User Map Flag Indicates whether BDM registers and ROM are mapped to addresses $FF00 to $FFFF in the standard 64-Kbyte address space. Used only ...
Page 122
STATUS — BDM Status Register Bit 7 6 ENBDM BDMACT RESET This register can be read or written by BDM commands or firmware. ENBDM — Enable BDM (permit active background debug mode BDM cannot be made ...
Page 123
Breakpoints Hardware breakpoints are used to debug software on the MC68HC912B32 by comparing actual ad- dress and data values to predetermined data in setup registers. A successful comparison will place the CPU in background debug mode (BDM) or initiate ...
Page 124
Breakpoints are not allowed if the BDM mode is already active. Active mode means the CPU is executing out of the BDM ROM. • BDM should not be entered from a breakpoint unless the ENABLE bit is set in ...
Page 125
Table 48 Breakpoint Address Range Control BK1ALE BK0ALE – 0 – – 1 – BRKCT1 — Breakpoint Control Register 1 Bit BKDBE BKMBH RESET This register is read/write in all modes. BKDBE — ...
Page 126
Table 49 Breakpoint Read/Write Control BK1RWE BK1RW BK0RWE – – – – – – BRKAH — Breakpoint Address Register, High Byte Bit 7 6 Bit 15 14 RESET These bits are used ...
Page 127
Instruction Tagging The instruction queue and cycle-by-cycle CPU activity can be reconstructed in real time or from trace history that was captured by a logic analyzer. However, the reconstructed queue cannot be used to stop the CPU at a ...
Page 128
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...