AT89C51ID2-IM ATMEL [ATMEL Corporation], AT89C51ID2-IM Datasheet
AT89C51ID2-IM
Available stocks
Related parts for AT89C51ID2-IM
AT89C51ID2-IM Summary of contents
Page 1
... Packages: PLCC44, VQFP44 Description AT89C51ID2 is a high performance CMOS Flash version of the 80C51 CMOS single chip 8-bit microcontroller. It contains a 64 Kbytes Flash memory block for program and for data. The 64 Kbytes Flash memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software ...
Page 2
... AT89C51ID2 2 The AT89C51ID2 retains all features of the Atmel 80C52 with 256 bytes of internal RAM, a 10-source 4-level interrupt controller and three timer/counters. In addition, the AT89C51ID2 has a Programmable Counter Array, an XRAM of 1792 bytes, a Hardware Watchdog Timer, SPI and Keyboard, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode) ...
Page 3
... IB-bus CPU Parallel I/O Ports & Timer 0 INT External Bus Ctrl Timer 1 Port 0 Port 1 Port 2 (2) (2) (2) (2) (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Alternate function of Port I2 AT89C51ID2 (1) (1) (1) (1) (1) Watch XRAM Dog PCA Keyboard Timer2 1792 x 8 POR PFD ...
Page 4
... SFR Mapping AT89C51ID2 4 The Special Function Registers (SFRs) of the AT89C51ID2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP • I/O port registers: P0, P1, P2, P3, PI2 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • ...
Page 5
... TWIX2 WDTX2 PCAX2 SIX2 - - - - ET2 PPCH PT2H PSH - PPCL PT2L PSL - - - - - - - - AT89C51ID2 RS0 GF1 GF0 PD IDL EXTRA XRS1 XRS0 AO M GF3 0 - DPS - - - - - - - CKS - SCLKT0 OscBEn OscAEn T2X2 T1X2 T0X2 ...
Page 6
... WatchDog Timer Program T2CON C8h Timer/Counter 2 control T2MOD C9h Timer/Counter 2 Mode Timer/Counter 2 Reload/Capture RCAP2H CBh High byte Timer/Counter 2 Reload/Capture RCAP2L CAh Low byte TH2 CDh Timer/Counter 2 High Byte TL2 CCh Timer/Counter 2 Low Byte AT89C51ID2 FPL3 FPL2 FPL1 FPL0 ...
Page 7
... CCAP3L5 CCAP3L4 CCAP4L7 CCAP4L6 CCAP4L5 CCAP4L4 FE/SM0 SM1 SM2 SPR2 SPEN SSDIS SPIF WCOL SSERR SPD7 SPD6 SPD5 AT89C51ID2 CCF3 CCF2 CCF1 - CPS1 CPS0 MAT0 TOG0 PWM0 MAT1 TOG1 PWM1 MAT2 TOG2 PWM2 MAT3 TOG3 PWM3 MAT4 TOG4 ...
Page 8
... KBLS 9Ch Keyboard Level Selector KBE 9Dh Keyboard Input Enable KBF 9Eh Keyboard Flag Register Table 13. EEPROM data Memory SFR Mnemonic Add Name EECON D2h EEPROM Data Control AT89C51ID2 SSCR2 SSPE SSSTA SSSTO SSC4 SSC3 SSC2 SSC1 SSD7 SSD6 ...
Page 9
... SSCS 0000 0000 1111 1000 TL0 TL1 TH0 0000 0000 0000 0000 0000 0000 DPL DPH 0000 0000 0000 0000 2/A 3/B 4/C Reserved AT89C51ID2 5/D 6/E 7/F CCAP3H CCAP4H XXXX XXXX XXXX XXXX CCAP3L CCAP4L XXXX XXXX XXXX XXXX CCAPM3 CCAPM4 X000 0000 X000 0000 TH2 ...
Page 10
... P0.4/AD4 38 P0.5/AD5 37 P0.6/AD6 36 P0.7/AD7 PI2.0/SCL 33 ALE/PROG 32 PSEN 31 P2.7/A15 30 P2.6/A14 29 P2.5/A13 RST 4 5 AT89C51ID2 6 VQFP44 1 P0.4/AD4 33 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 PI2.0/SCL 27 ALE/PROG ...
Page 11
... As inputs, Port 1 pins that are externally pulled 28, 29 19, 20 low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for AT89C51ID2 Port 1 include I/O P1.0: Input/Output I/O T2 (P1 ...
Page 12
... P4 P5.0 - P5.7 63 AT89C51ID2 12 Type VQFP64 Name and Function I/O CEX4: Capture/Compare External I/O for PCA module 4 I/O MOSI: SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. ...
Page 13
... I External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH. If security level 1 is programmed, EA will be internally latched on Reset. AT89C51ID2 permits a power This pin is an output when CC 13 ...
Page 14
... Oscillators Overview Registers AT89C51ID2 14 Two oscillators are available (for AT8xC51IxD2 devices only, the others part number provide only the main high frequency oscillator): • OSCA used for high frequency MHz • OSCB used for low frequency: 32.768 kHz Several operating modes are available and programmable by software: • ...
Page 15
... Reset Value = XXXX X0’HSB.OSC’’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable Table 18. CKRL Register CKRL - Clock Reload Register Bit Number Mnemonic Description Clock Reload Register: 7:0 CKRL Prescaler value Reset Value = 1111 1111b Not bit addressable AT89C51ID2 SCLKT0 OscBEn OscAEn ...
Page 16
... AT89C51ID2 16 Table 19. PCON Register PCON - Power Control Register (87h SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode Serial port Mode bit 0 6 SMOD0 Cleared to select SM0 bit in SCON register. ...
Page 17
... CKS = 0: OscB is selected for CPU. • CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1 and CKRL registers • CKS bit in CKSEL register selects either OscA or OscB • CKRL register determines the frequency of the OscA clock. AT89C51ID2 CLK PERIPH 0 CLK ...
Page 18
... Idle Modes Power Down Modes AT89C51ID2 18 • always possible to switch dynamically by software from OscA to OscB, and vice versa by changing CKS bit. • IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL) • IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 bit: • ...
Page 19
... CKRL = FFh: maximum frequency CLK CPU CLK PERIPH CLK CPU CLK PERIPH AT89C51ID2 CKS Selected Mode The CPU is off, OscA supplies the 1 IDLE MODE A peripherals, OscB can be disabled (OscBEn = 0) The CPU is off, OscB supplies the 0 IDLE MODE B peripherals, OscA can be disabled ...
Page 20
... Timer 0: Clock Inputs AT89C51ID2 20 – F and F , for CKRL 0xFF CLK CPU CLK PERIPH In X2 Mode Mode Figure 1. Timer 0: Clock Inputs FCLK PERIPH :6 T0 pin 0 1 Sub Clock ...
Page 21
... ALE disabling • Enhanced features on the UART and the timer 2 The AT89C51ID2 core needs only 6 clock periods per machine cycle. This feature called ‘X2’ provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. ...
Page 22
... Figure 4. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode AT89C51ID2 22 F OSC X2 Mode The X2 bit in the CKCON0 register (see Table 21) allows a switch from 12 clock periods per instruction to 6 clock periods and vice versa. At reset, the speed is set according to X2 bit of Hardware Security Byte (HSB). By default, Standard mode is active. Setting the X2 bit activates the X2 feature (X2 mode) ...
Page 23
... X2 to enable the individual peripherals’X2’ bits. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), Default setting cleared. Reset Value = 0000 000’HSB. X2’b (See “Hardware Security Byte”) Not bit addressable AT89C51ID2 SIX2 T2X2 T1X2 T0X2 ...
Page 24
... AT89C51ID2 24 Table 22. CKCON1 Register CKCON1 - Clock Control Register (AFh Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 - Reserved 1 - Reserved SPI (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). 0 SPIX2 Clear to select 6 clock periods per peripheral clock cycle ...
Page 25
... There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1.0 (see Table 23) that allows the program code to switch between them (Refer to Figure 5). 0 DPS DPTR1 DPH(83H) DPL(82H) AT89C51ID2 External Data Memory DPTR0 25 ...
Page 26
... AT89C51ID2 26 Table 23. AUXR1 register AUXR1- Auxiliary Register 1(0A2h ENBOOT Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Enable Boot Flash Cleared to disable boot ROM ...
Page 27
... DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. AT89C51ID2 27 ...
Page 28
... AT89C51ID2 devices have expanded RAM in external data space configurable up to 1792bytes (see Table 24.). The AT89C51ID2 has internal data memory that is mapped into four separate segments. The four segments are: 1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly addressable ...
Page 29
... The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data memory. The stack may not be located in the XRAM. The M0 bit allows to stretch the XRAM timings set, the read and write pulses are extended from clock periods. This is useful to access external slow peripherals. AT89C51ID2 29 ...
Page 30
... Registers AT89C51ID2 30 Table 24. AUXR Register AUXR - Auxiliary Register (8Eh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Pulse length ...
Page 31
... The Reset input can be used to force a reset pulse longer than the internal reset con- trolled by the Power Monitor. RST input has a pull-down resistor allowing power-on reset by simply connecting an external capacitor to V value and input characteristics are discussed in the Section “DC Characteristics” of the AT89C51ID2 datasheet. Figure 8. Reset Circuitry and Power-On Reset RST VSS a ...
Page 32
... RST pin. In order to properly propagate this pulse to the rest of the application in case of external capacitor or power-supply supervisor circuit resistor must be added as shown Figure 9. Figure 9. Recommended Reset Output Schematic VDD + RST VDD 1K RST VSS AT89C51ID2 To other on-board circuitry 4289B–8051–12/03 ...
Page 33
... This is achieved by applying an internal reset to them. By gen erating the the Power Monito r insures a correct start up whe n AT89C51ID2 is powered up. In order to startup and maintain the microcontroller in correct operating mode stabilized in the V ...
Page 34
... Figure 11. Power Fail Detect Vcc Reset Vcc AT89C51ID2 34 The Power fail detect monitor the supply generated by the voltage regulator and gener- ate a reset if this supply falls below a safety threshold as illustrated in the Figure 11 below. When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input ...
Page 35
... Timer 2 Auto-Reload Mode 4289B–8051–12/03 The Timer 2 in the AT89C51ID2 is the standard C52 Timer 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2 are cascaded controlled by T2CON (Table 25) and T2MOD (Table 26) registers. Timer 2 operation is similar to Timer 0 and Timer 1.C/T2 selects F (timer operation) or external pin T2 (counter operation) as the timer clock input ...
Page 36
... Programmable Clock- Output AT89C51ID2 36 Figure 12. Auto-Reload Mode Up/Down Counter (DCEN = 1) F CLK PERIPH : 6 In the clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock gen- erator (See Figure 13). The input clock increments TL2 at frequency F timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2 ...
Page 37
... Figure 13. Clock-Out Mode C/ FCLK PERIPH T2 T2EX AT89C51ID2 TR2 T2CON 2 TL2 TH (8-bit) (8-bit) RCAP2H RCAP2L (8-bit) (8-bit) Toggle Q D T2OE T2MOD EXF2 T2CON EXEN2 T2CON OVER- FLOW TIMER 2 INTERRUPT 37 ...
Page 38
... Registers AT89C51ID2 38 Table 25. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on Timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
Page 39
... Timer 2 Output Enable bit 1 T2OE Cleared to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit 0 DCEN Cleared to disable Timer 2 as up/down counter. Set to enable Timer 2 as up/down counter. Reset Value = XXXX XX00b Not bit addressable AT89C51ID2 T2OE 0 DCEN 39 ...
Page 40
... Programmable Counter Array PCA AT89C51ID2 40 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/capture modules ...
Page 41
... Figure 14. PCA Timer/Counter Fclk periph /6 Fclk periph / 2 T0 OVF P1.2 Idle 4289B–8051–12/03 CH CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 AT89C51ID2 To PCA modules overflow bit up counter CMOD ECF 0xD9 CCON 0xD8 41 ...
Page 42
... AT89C51ID2 42 Table 27. CMOD Register CMOD - PCA Counter Mode Register (D9h CIDL WDTE - Bit Bit Number Mnemonic Description Counter Idle Control 7 CIDL Cleared to program the PCA Counter to continue functioning during idle Mode. Set to program PCA to be gated off during idle. Watchdog Timer Enable ...
Page 43
... PCA Module 0 interrupt flag 0 CCF0 Must be cleared by software. Set by hardware when a match or capture occurs. Reset Value = 00X0 0000b Not bit addressable The watchdog timer function is implemented in module 4 (See Figure 17). The PCA interrupt system is shown in Figure 15. AT89C51ID2 CCF4 CCF3 CCF2 CCF1 1 ...
Page 44
... Figure 15. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 CMOD.0 AT89C51ID2 CCF4 CCF3 CCF2 CCF1 CCF0 ECCFn CCAPMn.0 ECF PCA Modules: each one of the five compare/capture modules has six possible func- tions. It can perform: • 16-bit Capture, positive-edge triggered • ...
Page 45
... Set to enable the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt Cleared to disable compare/capture flag CCFn in the CCON register to generate 0 CCF0 an interrupt. Set to enable compare/capture flag CCFn in the CCON register to generate an interrupt. Reset Value = X000 0000b Not bit addressable AT89C51ID2 CAPNn MATn TOGn PWMn 1 0 ...
Page 46
... AT89C51ID2 46 Table 30. PCA Module Modes (CCAPMn Registers) ECOMn CAPPn CAPNn MATn There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 31 & ...
Page 47
... CH Value Reset Value = 0000 0000b Not bit addressable Table 34. CL Register CL - PCA Counter Register Low (0E9h Bit Bit Number Mnemonic Description PCA Counter 7 Value Reset Value = 0000 0000b Not bit addressable AT89C51ID2 ...
Page 48
... Cex.n ECOMn 16-bit Software Timer/ Compare Mode AT89C51ID2 48 To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the mod- ule (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module's capture registers (CCAPnL and CCAPnH) ...
Page 49
... PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module's CCAPMn SFR must be set (See Figure 18). A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit. AT89C51ID2 CCON 0xD8 CCF3 ...
Page 50
... Figure 18. PCA High Speed Output Mode Write to Reset CCA PnL Write to CCAPnH 0 1 Enable Pulse Width Modulator Mode AT89C51ID2 CCF4 CCF3 CCF2 CCF1 CCF0 CCAPnH CCAPnL Match 16 bit comparator CH CL PCA counter/timer ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted match could happen. Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’ ...
Page 51
... Remember, the PCA timer is the time base for all modules; changing the time base for other modules would not be a good idea. Thus, in most appli- cations the first solution is the best option. This watchdog timer won’t generate a reset out on the reset pin. AT89C51ID2 CCAPnH CCAPnL “0” ...
Page 52
... Framing Error Detection AT89C51ID2 52 The serial I/O port in the AT89C51ID2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as a Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously ...
Page 53
... Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b AT89C51ID2 Data byte Ninth bit ...
Page 54
... Broadcast Address Reset Addresses AT89C51ID2 54 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB don’t-care bit; for slaves B and C, bit 1.To commu- nicate with slave A only, the master must send an address where bit 0 is clear (e. g. ...
Page 55
... The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Figure 23. Baud Rate Selection TIMER1 TIMER_BRG_RX 0 TIMER2 1 RCLK INT_BRG TIMER1 TIMER_BRG_TX 0 TIMER2 1 TCLK INT_BRG AT89C51ID2 Clock 1 RBCK ...
Page 56
... Internal Baud Rate Generator (BRG) Figure 24. Internal Baud Rate F PER BRR AT89C51ID2 56 Table 37. Baud Rate Selection Table UART TCLK RCLK (T2CON) (T2CON) (BDRCON When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register ...
Page 57
... Receive Interrupt flag Clear to acknowledge interrupt Set by hardware at the end of the 8th bit time in mode 0, see Figure 21. and Figure 22. in the other modes. Reset Value = 0000 0000b Bit addressable AT89C51ID2 REN TB8 RB8 SM1 Mode ...
Page 58
... UART Registers AT89C51ID2 58 Table 39. Example of Computed Value When X2=1, SMOD1=1, SPD=1 Baud Rates F = 16. 384 MHz OSC BRL 115200 247 57600 238 38400 229 28800 220 19200 203 9600 149 4800 43 Table 40. Example of Computed Value When X2=0, SMOD1=0, SPD=0 Baud Rates F = 16. 384 MHz ...
Page 59
... Table 43. SBUF Register SBUF - Serial Buffer Register for UART (99h Reset Value = XXXX XXXXb Table 44. BRL Register BRL - Baud Rate Reload Register for the internal baud rate generator, UART (9Ah Reset Value = 0000 0000b AT89C51ID2 ...
Page 60
... AT89C51ID2 60 Table 45. T2CON Register T2CON - Timer 2 Control Register (C8h TF2 EXF2 RCLK Bit Bit Number Mnemonic Timer 2 overflow Flag 7 TF2 Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1 ...
Page 61
... Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. AT89C51ID2 POF GF1 ...
Page 62
... AT89C51ID2 62 Table 47. BDRCON Register BDRCON - Baud Rate Control Register (9Bh Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit Reserved 6 - The value read from this bit is indeterminate. Do not set this bit Reserved ...
Page 63
... Individual Enable 4289B–8051–12/03 The AT89C51ID2 has a total of 10 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2), the serial port interrupt, SPI interrupt, Keyboard interrupt and the PCA global interrupt. These interrupts are shown in Figure 25 ...
Page 64
... Registers AT89C51ID2 64 The PCA interrupt vector is located at address 0033H, the SPI interrupt vector is located at address 0043H and Keyboard interrupt vector is located at address 004BH. All other vectors addresses are the same as standard C52 devices. Table 48. Priority Level Bit Values IPH low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’ ...
Page 65
... Timer 0 overflow interrupt Enable bit 1 ET0 Cleared to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt. External interrupt 0 Enable bit 0 EX0 Cleared to disable external interrupt 0. Set to enable external interrupt 0. Reset Value = 0000 0000b Bit addressable AT89C51ID2 ET1 EX1 ET0 1 0 EX0 65 ...
Page 66
... AT89C51ID2 66 Table 50. IPL0 Register IPL0 - Interrupt Priority Register (B8h PPCL PT2L Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA interrupt Priority bit 6 PPCL Refer to PPCH for priority level. Timer 2 overflow interrupt Priority bit ...
Page 67
... Timer 0 overflow interrupt Priority High bit PT0HPT0LPriority Level 0 0Lowest 1 PT0H 1Highest External interrupt 0 Priority High bit PX0H PX0LPriority Level 0 0Lowest 0 PX0H 1Highest Reset Value = X000 0000b Not bit addressable AT89C51ID2 PSH PT1H PX1H PT0H 1 0 PX0H 67 ...
Page 68
... AT89C51ID2 68 Table 52. IEN1 Register IEN1 - Interrupt Enable Register (B1h Bit Bit Number Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved SPI interrupt Enable bit Cleared to disable SPI interrupt. 2 ESPI Set to enable SPI interrupt. TWI interrupt Enable bit 1 ETWI Cleared to disable TWI interrupt. ...
Page 69
... SPI interrupt Priority bit 2 SPIL Refer to SPIH for priority level. TWI interrupt Priority bit 1 TWIL Refer to TWIH for priority level. Keyboard interrupt Priority bit 0 KBDL Refer to KBDH for priority level. Reset Value = XXXX X000b Bit addressable AT89C51ID2 SPIL TWIL 0 KBDL 69 ...
Page 70
... AT89C51ID2 70 Table 55. IPH1 Register IPH1 - Interrupt Priority High Register (B3h Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...
Page 71
... Polling Priority Interrupt Source Keyboard AT89C51ID2 Interrupt Request Reset INT0 IE0 Timer 0 TF0 INT1 IE1 Timer 1 IF1 UART RI+TI Timer 2 TF2+EXF2 PCA CF + CCFn (n = 0-4) KBDIT TWI TWIIT SPI SPIIT Vector Address 0000h ...
Page 72
... Idle mode. The contents of the status of the Port pins during Idle mode is detailed in Table 57. To enter Idle mode, set the IDL bit in PCON register (see Table 58). The AT89C51ID2 enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that sets IDL bit is the last instruction executed ...
Page 73
... Take care, however, that VDD is not reduced until Power-Down mode is invoked. To enter Power-Down mode, set PD bit in PCON register. The AT89C51ID2 enters the Power-Down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. ...
Page 74
... AT89C51ID2 74 pins, the instruction immediately following the instruction that activated the Power-Down mode should not write to a Port pin or to the external RAM. Note: Exit from power-down by reset redefines all the RAM content. Table 57. Pin Conditions in Special Operating Modes Mode Port 0 ...
Page 75
... Set to activate the Power-Down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. 0 IDL Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. Reset Value= XXXX 0000b AT89C51ID2 POF GF1 GF0 1 0 ...
Page 76
... Power Reduction Mode AT89C51ID2 76 The AT89C51ID2 implements a keyboard interface allowing the connection matrix keyboard based on 8 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1 and allow to exit from idle and power down modes. ...
Page 77
... Set by hardware when the Port line 0 detects a programmed level. It generates a 0 KBF0 Keyboard interrupt request if the KBIE. 0 bit in KBIE register is set. Must be cleared by software. Reset Value= 0000 0000b This register is read only access, all flags are automatically cleared by reading the register. AT89C51ID2 KBF4 KBF3 KBF2 KBF1 ...
Page 78
... AT89C51ID2 78 Table 60. KBE Register KBE-Keyboard Input Enable Register (9Dh KBE7 KBE6 KBE5 Bit Bit Number Mnemonic Description Keyboard line 7 Enable bit 7 KBE7 Cleared to enable standard I/O pin. Set to enable KBF. 7 bit in KBF register to generate an interrupt request. Keyboard line 6 Enable bit 6 KBE6 Cleared to enable standard I/O pin ...
Page 79
... Cleared to enable a low level detection on Port line 1. Set to enable a high level detection on Port line 1. Keyboard line 0 Level Selection bit 0 KBLS0 Cleared to enable a low level detection on Port line 0. Set to enable a high level detection on Port line 0. Reset Value= 0000 0000b AT89C51ID2 KBLS4 KBLS3 KBLS2 KBLS1 ...
Page 80
... Interface (TWI) AT89C51ID2 80 This section describes the 2-wire interface. The 2-wire bus is a bi-directional 2-wire serial communication standard designed primarily for simple but efficient integrated circuit (IC) control. The system is comprised of two lines, SCL (Serial Clock) and SDA (Serial Data) that carry information between the ICs connected to them. The serial data transfer is limited to 400 Kbit/s in standard mode ...
Page 81
... Stage 4289B–8051–12/03 SSADR Address Register Comparator SSDAT Shift Register Arbitration & Sink Logic Timing & Control logic Serial clock generator Timer 1 overflow Control Register SSCON Status Status Decoder Bits SSCS Status Register AT89C51ID2 8 ACK CLK PERIPH Interrupt ...
Page 82
... Description AT89C51ID2 82 The CPU interfaces to the 2-wire logic via the following four 8-bit special function regis- ters: the Synchronous Serial Control register (SSCON; Table 71), the Synchronous Serial Data register (SSDAT; Table 72), the Synchronous Serial Control and Status reg- ister (SSCS; Table 73) and the Synchronous Serial Address register (SSADR Table 76). ...
Page 83
... The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt routine must load SSDAT with the 7-bit slave address and the data direction bit (SLA+R). The serial interrupt flag SI must then be cleared before the serial transfer can continue. AT89C51ID2 STO SI AA ...
Page 84
... Slave Receiver Mode Slave Transmitter Mode AT89C51ID2 84 When the slave address and the direction bit have been transmitted and an acknowl- edgement bit has been received, the serial interrupt flag is set again and a number of status code in SSCS are possible. There are 40h, 48h or 38h for the master mode and also 68h, 78h or B0h if the slave mode was enabled (AA=logic 1) ...
Page 85
... AT89C51ID2 MHz F divided by OSCA OSCA 62.5 256 71.5 224 83 192 100 160 - Unused 133.3 120 266 · (256 - reload valueTimer 1) 0.67 <. < 83 (reload value range: 0-254 in mode 2) 85 ...
Page 86
... Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave From master to slave From slave to master AT89C51ID2 86 MT SLA W A Data 18h A P 20h Other master ...
Page 87
... AT89C51ID2 Next Action Taken by Two-wire Hardware X SLA+W will be transmitted. SLA+W will be transmitted. X SLA+R will be transmitted. X Logic will switch to master receiver mode Data byte will be transmitted. X Repeated START will be transmitted. X STOP condition will be transmitted and SSSTO flag X will be reset ...
Page 88
... Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or acknowledge bit Arbitration lost and addressed as slave From master to slave From slave to master AT89C51ID2 88 MR Data 50h 40h A P 48h Other master ...
Page 89
... AT89C51ID2 Next Action Taken by Two-wire Hardware X SLA+R will be transmitted. SLA+R will be transmitted. X SLA+W will be transmitted. X Logic will switch to master transmitter mode. Two-wire bus will be released and not addressed X slave mode will be entered. A START condition will be transmitted when the bus X becomes free ...
Page 90
... Reception of the general call address and one or more data bytes. Last data byte received is not acknowledged. Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT89C51ID2 90 S SLA W A 60h A 68h General Call ...
Page 91
... Read data byte or Read data byte AT89C51ID2 AA Next Action Taken By 2-wire Software Data byte will be received and NOT ACK will be 0 returned Data byte will be received and ACK will be 1 returned Data byte will be received and NOT ACK will be ...
Page 92
... Previously addressed with general call; data has been 98h received; NOT ACK has been returned A STOP condition or repeated START condition has been A0h received while still addressed as slave AT89C51ID2 92 Application Software Response To/from SSDAT To SSCON STA STO SI Read data byte ...
Page 93
... Load data byte X 0 Load data byte Load data byte X 0 Load data byte Load data byte X 0 AT89C51ID2 Data A C0h B8h All 1’s A C8h SI AA Next Action Taken By 2-wire Software Last data byte will be transmitted and NOT ACK 0 ...
Page 94
... Data byte in SSDAT has been C0h transmitted; NOT ACK has been received Last data byte in SSDAT has C8h been transmitted (AA=0); ACK has been received AT89C51ID2 94 Application Software Response To/from SSDAT To SSCON STA STO No SSDAT action SSDAT action or ...
Page 95
... Address bit 6 or Data bit 6. 5 SD5 Address bit 5 or Data bit 5. 4 SD4 Address bit 4 or Data bit 4. 3 SD3 Address bit 3 or Data bit 3. 2 SD2 Address bit 2 or Data bit 2. AT89C51ID2 STO SI AA CR1 SD4 SD3 SD2 SD1 4 ...
Page 96
... AT89C51ID2 96 Bit Bit Number Mnemonic Description 1 SD1 Address bit 1 or Data bit 1. 0 SD0 Address bit 0 (R/W) or Data bit 0. Table 73. SSCS (094h) read - Synchronous Serial Control and Status Register SC4 SC3 SC2 Table 74. SSCS Register: Read Mode - Reset Value = F8h ...
Page 97
... Bit Bit Number Mnemonic Description General Call bit 0 GC Clear to disable the general call address recognition. Set to enable the general call address recognition. AT89C51ID2 97 ...
Page 98
... Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) AT89C51ID2 98 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI Module include the following: • ...
Page 99
... SPR0 AT89C51ID2 . Clock Rate Baud Rate Divisor (BD CLK PERIPH F /4 CLK PERIPH F /8 CLK PERIPH F /16 CLK PERIPH F /32 CLK PERIPH F /64 CLK PERIPH F /128 CLK PERIPH Don’t Use (2) ...
Page 100
... Functional Description Operating Modes AT89C51ID2 100 Figure 37 shows a detailed structure of the SPI Module. Figure 37. SPI Module Block Diagram FCLK PERIPH /4 Clock /8 /16 Divider /32 /64 /128 Clock Select SPR2 SPEN SSDIS SPI Interrupt Request The Serial Peripheral Interface can be configured in one of the two modes: Master mode or Slave mode ...
Page 101
... The SPI Module should be configured as a Slave before it is enabled (SPEN set). 3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). AT89C51ID2 MISO 8-bit Shift register MOSI SCK SS ...
Page 102
... Figure 40. Data Transmission Format (CPHA = 1) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 41. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) AT89C51ID2 102 MSB bit6 bit5 bit4 MSB bit6 bit5 bit4 1 2 ...
Page 103
... SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests. When SSDIS is set, no MODF interrupt request is generated. Figure 42 gives a logical view of the above statements. AT89C51ID2 Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) ...
Page 104
... Registers Serial Peripheral Control Register (SPCON) AT89C51ID2 104 Figure 42. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request MODF SPI Receiver/error CPU Interrupt Request SSDIS There are three registers in the Module that provide control, status and data storage functions. These registers are describes in the following paragraphs. • ...
Page 105
... Set by hardware to indicate that the SS pin is at inappropriate logic level. Reserved 3 - The value read from this bit is indeterminate. Do not set this bit Reserved 2 - The value read from this bit is indeterminate. Do not set this bit. AT89C51ID2 SPR1 SPR0 Serial Peripheral Rate CLK PERIPH 0 ...
Page 106
... Serial Peripheral DATa Register (SPDAT) AT89C51ID2 106 Bit Bit Number Mnemonic Description Reserved 1 - The value read from this bit is indeterminate. Do not set this bit. Reserved 0 - The value read from this bit is indeterminate. Do not set this bit. Reset Value = 00X0 XXXXb Not Bit addressable The Serial Peripheral Data Register (Table 81 read/write buffer for the receive data register ...
Page 107
... WDTRST - Watchdog Reset Register (0A6h Reset Value = XXXX XXXXb Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. AT89C51ID2 , where T CLK PERIPH 7 counter has been added to extend the Time-out = 12MHz. To manage this feature, refer to OSCA ...
Page 108
... WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT89C51ID2 while in Idle mode, the user should always set up a timer that will periodi- cally exit Idle, service the WDT, and re-enter Idle mode. ...
Page 109
... Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the AT89C51ID2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 84 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. ...
Page 110
... Power-off Flag AT89C51ID2 110 The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced still applied to the device and could be generated for example by an exit from CC power-down ...
Page 111
... EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that the EEPROM segment is not available for reading or writing. • The end of programming is indicated by a hardware clear of the EEBUSY flag. Figure 43 represents the optimal write sequence to the on-chip EEPROM data memory. AT89C51ID2 111 ...
Page 112
... AT89C51ID2 112 Figure 43. Recommended EEPROM Data Write Sequence EEPROM Data Write EEPROM Data Mapping EECON = 02h (EEE=1) Exec: MOVX @DPTR, A EECON = 00h (EEE=0) Sequence EEBusy Cleared? Save & Disable IT EA= 0 Data Write DPTR= Address ACC= Data EEPROM Mapping Restore IT Last Byte to Load? 4289B– ...
Page 113
... Set bit EEE of EECON register • Execute a MOVX A, @DPTR • Clear bit EEE of EECON register • Restore interrupts. Figure 44. Recommended EEPROM Data Read Sequence AT89C51ID2 EEPROM Data Read Sequence EEBusy Cleared? Save & Disable IT EA= 0 EEPROM Data Mapping EECON = 02h (EEE=1) ...
Page 114
... Registers AT89C51ID2 114 Table 86. EECON Register EECON (0D2h) EEPROM Control Register Bit Bit Number Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Enable EEPROM Space bit Set to map the EEPROM space during MOVX instructions (Write or Read to ...
Page 115
... ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable AT89C51ID2 XRS2 XRS1 XRS0 EXTRAM ...
Page 116
... EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51ID2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. ...
Page 117
... Software registers are in a special page of the Flash memory which can be accessed through the API or with the parallel programming modes. This page, called "Extra Flash Memory", is not in the internal Flash program memory addressing space. The only hardware register of the AT89C51ID2 is called Hardware Security Byte (HSB). Table 88. Hardware Security Byte (HSB ...
Page 118
... Default Values Software Registers AT89C51ID2 118 Table 89. Program Lock Bits Program Lock Bits Security level LB0 LB1 LB2 Protection description program lock features enabled. MOVC instruction executed from external program memory is disabled from fetching code bytes from internal memory sampled and latched on reset, and further parallel programming of the on chip code memory is disabled ...
Page 119
... The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 93. AT89C51ID2 Default value Description FCh 101x 1011b 0FFh FFh 58h ATMEL D7h C51 X2, Electrically Erasable ECh AT89C51ID2 64KB AT89C51ID2 64KB, Revision EFh LB1 0 LB0 119 ...
Page 120
... X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. AT89C51ID2 parts are delivered in standard with the ISP rom bootloader. After ISP or parallel programming, the possible contents of the Flash memory are sum- marized on the figure below: ...
Page 121
... Flash memory. Furthermore, all accesses and routines can be called from the user application. Figure 46. Diagram Context Description Bootloader ISP : In-System Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte AT89C51ID2 Flash memory 121 ...
Page 122
... Functional Description Figure 47. Bootloader Functional Description Exernal host with Specific Protocol Communication AT89C51ID2 122 ISP Communication Management Flash Memory Management Flash Memory On the above diagram, the on chip bootloader processes are: • ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device ...
Page 123
... The Boot Loader Jump Bit forces the application execution. BLJB = 0 => Boot loader execution. BLJB = 1 => Application execution The BLJB is a fuse bit in the Hardware Byte. BLJB That can be modified by hardware (programmer software (API). Note: The BLJB test is perform by hardware to prevent any program execution.. AT89C51ID2 Purpose 123 ...
Page 124
... AT89C51ID2 124 The Software Boot Vector contains the high address of custumer bootloader stored in the application. SBV = FCh (default value custumer bootloader in user Flash. SBV Note: The costumer bootloader is called by JMP [SBV]00h instruction. Purpose 4289B–8051–12/03 ...
Page 125
... ENBOOT bit (AUXR1) is cleared Yes (PSEN = and ALE =1 or not connected) FCON = 00h Hardware condition? FCON = F0h BLJB=1 BLJB!= 0 ENBOOT=0 ? BLJB=0 ENBOOT=1 F800h yes = hardware boot FCON = 00h ? BSB = 00h ? SBV = FCh ? USER BOOT LOADER PC= [SBV]00h AT89C51ID2 conditions Atmel BOOT LOADER 125 ...
Page 126
... ISP Protocol Description Physical Layer Frame Description AT89C51ID2 126 The UART used to transmit information has the following configuration: • Character: 8-bit data • Parity: none • Stop: 2 bits • Flow control: none • Baudrate: autobaud is performed by the bootloader to compute the baudrate choosen by the host ...
Page 127
... Write level 2 allowed Read only access allowed Read only access allowed Allowed Not allowed Allowed Allowed AT89C51ID2 Level 1 Any access not allowed Any access not allowed Any access not allowed Read only access allowed Read only access allowed Read only access allowed ...
Page 128
... Full Chip Erase Checksum Error AT89C51ID2 128 The ISP command "Full Chip Erase" erases all User Flash memory (fills with FFh) and sets some bytes used by the bootloader at their default values: • BSB = FFh • SBV = FCh • SSB = FFh and finally erase the Software Security Bits The Full Chip Erase does not affect the bootloader. When a checksum error is detected send ‘ ...
Page 129
... This information is then used to pro- gram the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the AT89C51ID2 to establish the baud rate. Table show the autobaud capability. ...
Page 130
... Baudrate (kHz) 1.8432 4800 OK 9600 OK 19200 OK 38400 - 57600 - 115200 - Command Data Stream Protocol Figure 52. Command Flow Host Sends first character of the Frame Sends frame (made of 2 ASCII characters per byte) Echo analysis AT89C51ID2 130 2 2.4576 All commands are sent using the same flow ...
Page 131
... BOOTLOADER : 02 0000 F5 HOST : 03 0000 BOOTLOADER : 03 0000 AT89C51ID2 Bootloader Wait Write Command Checksum error Send Checksum error NO_SECURITY Send Security error Wait Programming ...
Page 132
... Wait Checksum Error COMMAND ABORTED Wait COMMAND_OK OR COMMAND FINISHED Wait Address not erased COMMAND FINISHED Example AT89C51ID2 132 Blank Check Command ’X’ & CR & LF ’.’ & CR & LF address & CR & HOST : 05 0000 04 0000 7FFF 01 78 BOOTLOADER : 05 0000 04 0000 7FFF 01 78 ...
Page 133
... Display Command ’X’ & CR & LF Send Checksum Error ’L’ & CR & LF Send Security Error Complet Frame "Address = " "Reading value" CR & LF AT89C51ID2 Bootloader Wait Display Command Checksum error RD_WR_SECURITY Read Data All data read Send Display Data All data read ...
Page 134
... COMMAND ABORTED OR Wait Security Error COMMAND ABORTED Wait Value of Data COMMAND FINISHED AT89C51ID2 134 HOST : 05 0000 04 0000 0020 00 D7 BOOTLOADER : 05 0000 04 0000 0020 00 D7 ...
Page 135
... F0 BOOTLOADER : 02 0000 Value . HOST : 02 0000 BOOTLOADER : 02 0000 Value . CR LF AT89C51ID2 135 ...
Page 136
... ISP Commands Summary Table 96. ISP Commands Summary Command 00h 03h 04h AT89C51ID2 136 Command Name data[0] Program Data 01h 03h 04h 05h Write Function 06h 07h 0Ah Data[0:1] = start address Data [2:3] = end address Display Function Data[4] = 00h -> Display data Data[4] = 01h -> Blank check Data[4] = 02h -> ...
Page 137
... Table 96. ISP Commands Summary (Continued) Command 05h 07h 4289B–8051–12/03 Command Name data[0] 00h Read Function 07h 0Bh 0Eh 0Fh Program EEPROM data AT89C51ID2 data[1] Command Effect 00h Manufacturer Id 01h Device Id #1 02h Device Id #2 03h Device Id #3 00h Read SSB 01h ...
Page 138
... XXh READ SBV 07h XXh AT89C51ID2 138 Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface, PGM_MTP. The programming functions are selected by setting up the microcontroller’ ...
Page 139
... DPL = 01h XXh ACC = ID2 XXXXh XXh ACC = Boot_Version AT89C51ID2 Command Effect Program up to 128 bytes in user Flash. Remark: number of bytes to program is limited such as the Flash write remains in a single 128 bytes page. Hence, when ACC is 128, valid values of DPL are 00h, or, 80h. ...
Page 140
... V Output Low Voltage, port 0, ALE, PSEN OL1 V Output High Voltage, ports AT89C51ID2 140 Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi- tions above those indicated in the operational sections of this specification is not implied ...
Page 141
... 1 (5) 50 200 RST = V (see Figure 58 must be externally limited as follows: OL may exceed the related specification. Pins are not guaranteed to sink current greater OL AT89C51ID2 Max Unit 250 k - -650 150 A 0.4 x Frequency (MHz ...
Page 142
... AT89C51ID2 142 Figure 57. I Test Condition, Active Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 58. I Test Condition, Idle Mode RST EA (NC) XTAL2 CLOCK XTAL1 SIGNAL V SS Figure 59. I Test Condition, Power-down Mode ...
Page 143
... Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV T ALE to PSEN LLPL T PSEN Pulse Width PLPH T PSEN to Valid Instruction In PLIV T Input Instruction Hold After PSEN PXIX T Input Instruction Float After PSEN PXIZ T Address to Valid Instruction In AVIV T PSEN Low to Address Float PLAZ AT89C51ID2 143 ...
Page 144
... AT89C51ID2 144 Table 99. AC Parameters for a Fix Clock Symbol -M Min LHLL T 5 AVLL T 5 LLAX T LLIV T 5 LLPL T 50 PLPH T PLIV T 0 PXIX T PXIZ T AVIV T PLAZ Table 100. AC Parameters for a Variable Clock Standard Symbol Type Clock T Min LHLL ...
Page 145
... ALE LLWL T Address AVWL T Data Valid to WR Transition QVWX T Data Set- High QVWH T Data Hold After WR WHQX T RD Low to Address Float RLAZ High to ALE high WHLH AT89C51ID2 CLCL T PXAV T PXIZ A0-A7 INSTR IN ADDRESS A8-A15 145 ...
Page 146
... AT89C51ID2 146 Table 102. AC Parameters for a Fix Clock -M Symbol Min T 125 RLRH T 125 WLWH T RLDV T 0 RHDX T RHDZ T LLDV T AVDV T 45 LLWL T 70 AVWL T 5 QVWX T 155 QVWH T 10 WHQX T 0 RLAZ T 5 WHLH Table 103. AC Parameters for a Variable Clock Standard ...
Page 147
... XLXL T Output data set-up to clock rising edge QVHX T Output data hold after clock rising edge XHQX T Input data hold after clock rising edge XHDX T Clock rising edge to input data valid XHDV AT89C51ID2 T WHLH T WLWH T T WHQX QVWH DATA OUT T WHLH T RLRH ...
Page 148
... Shift Register Timing Waveforms 0 INSTRUCTION ALE CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Waveforms AT89C51ID2 148 Table 105. AC Parameters for a Fix Clock -M Symbol Min T 300 XLXL T 200 QVHX T 30 XHQX T 0 XHDX T XHDV Table 106. AC Parameters for a Variable Clock ...
Page 149
... For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V occurs mA Valid in normal clock mode mode XTAL2 must be changed to XTAL2/2. AT89C51ID2 0 0 0.5 for a logic “1” and 0.45V for a logic “0”. ...
Page 150
... This propagation delay is dependent on variables such as temperature and pin loading. Propaga- tion also varies from output to output and component. Typically though (T delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. AT89C51ID2 150 STATE5 STATE6 ...
Page 151
... Ordering Information Change Log for 4289A - 09/03 to 4289B - 12/03 4289B–8051–12/03 Table 107. Possible Order Entries Supply Part Number Voltage AT89C51ID2-SLSIM 2.7V-5.5V AT89C51ID2-RLTIM 1. Improvement of explanations throughout the document. AT89C51ID2 Temperature Range Package Packing PLCC44 Stick Industrial VQFP44 Tray Product Marking AT89C51ID2-IM AT89C51ID2-IM 151 ...
Page 152
... Packaging Information PLCC44 AT89C51ID2 152 4289B–8051–12/03 ...
Page 153
... VQFP44 4289B–8051–12/03 AT89C51ID2 153 ...
Page 154
... Table of Contents AT89C51ID2 i Features................................................................................................. 1 Description ............................................................................................ 1 Block Diagram....................................................................................... 3 SFR Mapping......................................................................................... 4 Pin Configurations.............................................................................. 10 Oscillators ........................................................................................... 14 Overview............................................................................................................. 14 Registers............................................................................................................. 14 Functional Block Diagram................................................................................... 17 ............................................................................................................................ 17 Operating Modes ................................................................................................ 17 Design Considerations........................................................................................ 19 Timer 0: Clock Inputs.......................................................................................... 20 Enhanced Features............................................................................. 21 X2 Feature .......................................................................................................... 21 Dual Data Pointer Register DPTR...................................................... 25 Expanded RAM (XRAM) ..................................................................... 28 Registers............................................................................................................. 30 Reset .................................................................................................... 31 Introduction ......................................................................................................... 31 Reset Input ......................................................................................................... 31 Reset Output ...
Page 155
... Signal Description............................................................................................... 98 Functional Description ...................................................................................... 100 Hardware Watchdog Timer .............................................................. 107 Using the WDT ................................................................................................. 107 WDT During Power Down and Idle................................................................... 108 ONCE(TM) Mode (ON Chip Emulation) ........................................... 109 Power-off Flag................................................................................... 110 EEPROM Data Memory..................................................................... 111 Write Data......................................................................................................... 111 Read Data......................................................................................................... 113 Registers........................................................................................................... 114 AT89C51ID2 ii ...
Page 156
... AT89C51ID2 iii Reduced EMI Mode........................................................................... 115 Flash Memory.................................................................................... 116 Features............................................................................................................ 116 Flash Programming and Erasure ...................................................................... 116 Flash Registers and Memory Map.................................................................... 117 Flash Memory Status........................................................................................ 120 Memory Organization ....................................................................................... 120 Bootloader Architecture .................................................................................... 121 ISP Protocol Description................................................................................... 126 Functional Description ...................................................................................... 127 Flow Description ............................................................................................... 129 API Call Description ...
Page 157
Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...