AT89C51CC03CA-RLTUM Atmel, AT89C51CC03CA-RLTUM Datasheet

IC 8051 MCU 64K FLASH 44-VQFP

AT89C51CC03CA-RLTUM

Manufacturer Part Number
AT89C51CC03CA-RLTUM
Description
IC 8051 MCU 64K FLASH 44-VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheet

Specifications of AT89C51CC03CA-RLTUM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Processor Series
AT89x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
UART, SPI
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
36
Number Of Timers
2
Operating Supply Voltage
3 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Package
44VQFP
Device Core
8051
Family Name
AT89
Maximum Speed
60 MHz
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
AT89C51CC03CA-RLTUM
Manufacturer:
ADI
Quantity:
141
Price:
Features
1.
80C51 Core Architecture
256 Bytes of On-chip RAM
2048 Bytes of On-chip ERAM
64K Bytes of On-chip Flash Memory
2K Bytes of On-chip Flash for Bootloader
2K Bytes of On-chip EEPROM
Read/Write Cycle: 100K
Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
High-speed Architecture
Five Ports: 32 + 4 Digital I/O Lines
Five-channel 16-bit PCA with
Double Data Pointer
21-bit WatchDog Timer (7 Programmable Bits)
A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs
SPI Interface, (PLCC52 and VPFP64 packages only)
Full CAN Controller
– Data Retention: 10 Years at 85°C
– Read/Write Cycle: 100K
– In Standard Mode:
– In X2 mode (6 Clocks/machine cycle)
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
– Fully Compliant with CAN Rev 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 15 Independent Message Objects
– Supports
– 1-Mbit/s Maximum Transfer Rate at 8 MHz
– Readable Error Counters
– Programmable Link to On-chip Timer for Time Stamping and Network
– Independent Baud Rate Prescaler
– Data, Remote, Error and Overload Frame Handling
Synchronization
40 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
20 MHz (Vcc 3V to 5.5V, both Internal and external code execution)
30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)
– Each Message Object Programmable on Transmission or Reception
– Individual Tag and Mask Filters up to 29-bit Identifier/Channel
– 8-byte Cyclic Data Register (FIFO)/Message Object
– 16-bit Status and Control Register/Message Object
– 16-bit Time-Stamping Register/Message Object
– CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
– Access to Message Object Control and Data Registers Via SFR
– Programmable Reception Buffer Length Up To 15 Message Objects
– Priority Management of Reception of Hits on Several Message Objects at the
Same Time (Basic CAN Feature)
– Priority Management for Transmission
– Message Object Overrun Interrupt
– Time Triggered Communication
– Autobaud and Listening Mode
– Programmable Automatic Reply Mode
At BRP = 1 sampling point will be fixed.
(1)
Crystal Frequency in X2 Mode
Enhanced 8-bit
MCU with CAN
Controller and
Flash Memory
AT89C51CC03
Rev. 4182O–CAN–09/08

Related parts for AT89C51CC03CA-RLTUM

AT89C51CC03CA-RLTUM Summary of contents

Page 1

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 2048 Bytes of On-chip ERAM • 64K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K • 2K Bytes of On-chip ...

Page 2

On-chip Emulation Logic (Enhanced Hook System) • Power Saving Modes – Idle Mode – Power-down Mode • Power Supply: 3 volts to 5.5 volts • Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C) • Packages: VQFP44, PLCC44, ...

Page 3

Pin Configuration 4182O–CAN–09/08 P1.4/AN4/CEX1 7 P1.5/AN5/CEX2 8 P1.6/AN6/CEX3 9 P1.7/AN7/CEX4 P3.0/RxD 12 PLCC44 P3.1/TxD 13 P3.2/INT0 14 P3.3/INT1 15 P3.4/T0 16 P3.5/ P1.4/AN4/CEX1 1 P1.5/AN5/CEX2 2 P1.6/AN6/CEX3 3 P1.7/AN7/CEX4 4 ...

Page 4

AT89C51CC03 P1.4/AN4/CEX1 8 P1.5/AN5/CEX2 9 P1.6/AN6/CEX3 10 P1.7/AN7/CEX4 PLCC52 P3.0/RxD 14 P4.3/SCK 15 16 P3.1/TxD P3.2/INT0 17 P3.3/INT1 18 P3.4/T0 19 P3.5/T1/ ...

Page 5

Pin Name Type Description VSS GND Circuit ground TESTI I Must be connected to VSS VCC Supply Voltage VAREF Reference Voltage for ADC VAGND Reference Ground for ADC P0.0:7 I/O Port 8-bit open drain bi-directional I/O port. ...

Page 6

Pin Name Type Description P3.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs ...

Page 7

Pin Name Type Description Reset: RESET I/O A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to ...

Page 8

Port 0 and Port 2 AT89C51CC03 8 Figure 1. Port 1, Port 3 and Port 4 Structure READ LATCH INTERNAL D P1.X Q BUS P3.X P4.X WRITE LATCH CL TO LATCH READ PIN Note: The internal pull-up can be disabled ...

Page 9

Read-Modify-Write Instructions 4182O–CAN–09/08 Figure 3. Port 2 Structure ADDRESS HIGH/ CONTROL READ LATCH INTERNAL BUS D Q P2.X LATCH WRITE TO LATCH READ PIN Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus ...

Page 10

Quasi-Bidirectional Port Operation AT89C51CC03 10 write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. ...

Page 11

SFR Mapping Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH 83h MSB of DPTR Mnemonic ...

Page 12

Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WatchDog Timer WDTRST A6h Reset WatchDog Timer WDTPRG A7h Program Mnemonic Add Name ...

Page 13

Mnemonic Add Name Interrupt Enable IEN0 A8h Control 0 Interrupt Enable IEN1 E8h Control 1 Interrupt Priority IPL0 B8h Control Low 0 Interrupt Priority IPH0 B7h Control High 0 Interrupt Priority IPL1 F8h Control Low 1 Interrupt Priority IPH1 F7h ...

Page 14

Mnemonic Add Name CAN Interrupt CANIE2 C3h Enable Channel byte 2 CAN Status CANSIT1 BAh Interrupt Channel byte1 CAN Status CANSIT2 BBh Interrupt Channel byte2 CAN Timer CANTCON A1h TPRESC 7 Control CANTIMH ADh CAN Timer high CANTIML ACh CAN ...

Page 15

Mnemonic Add Name CAN Identifier Tag byte 4(PartA) CANIDT4 BFh CAN Identifier Tag byte 4(PartB) CAN Identifier Mask byte 1(PartA) CANIDM1 C4h CAN Identifier Mask byte 1(PartB) CAN Identifier Mask byte 2(PartA) CANIDM2 C5h CAN Identifier Mask byte 2(PartB) CAN ...

Page 16

Table 1. SFR Mapping (2) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 00xx x000 PSW FCON D0h 0000 ...

Page 17

Clock Description 4182O–CAN–09/08 The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power consumption while ...

Page 18

Figure 5. Clock CPU Generation Diagram Hardware byte CKCON.0 XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 SPIX2 CANX2 CKCON0.7 CKCON1.0 AT89C51CC03 18 X2B PCON.0 On RESET IDL X2 ÷ ÷ 2 ÷ ...

Page 19

Figure 6. Mode Switching Waveforms XTAL1 XTAL1/2 X2 bit CPU clock STD Mode Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a ...

Page 20

Registers AT89C51CC03 20 Table 2. CKCON0 Register CKCON0 (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to ...

Page 21

Table 3. CKCON1 Register CKCON1 (S:9Fh) Clock Control Register Bit Bit Number Mnemonic Description Reserved 7-1 - The value read from these bits is indeterminate. Do not set these bits. (1) SPI clock Clear to ...

Page 22

Data Memory AT89C51CC03 22 The AT89C51CC03 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: • the lower 128 Bytes RAM segment. • the upper 128 Bytes RAM segment. • the expanded ...

Page 23

Internal Space Lower 128 Bytes RAM Upper 128 Bytes RAM Expanded RAM 4182O–CAN–09/08 The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh using direct or indirect addressing modes. The lowest 32 Bytes are ...

Page 24

External Space Memory Interface External Bus Cycles AT89C51CC03 24 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE). Figure 10 shows the structure of the ...

Page 25

Figure 11. External Data Read Waveforms CPU Clock ALE RD#1 P0 DPL Notes: 1. RD# signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. ...

Page 26

Dual Data Pointer Description Application AT89C51CC03 26 The AT89C51CC03 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by ...

Page 27

Registers 4182O–CAN–09/08 Table 6. PSW Register PSW (S:8Eh) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 AC ...

Page 28

AT89C51CC03 28 Bit Bit Number Mnemonic Description ERAM size: Accessible size of the ERAM XRS 2:0 ERAM size 000 256 Bytes 001 512 Bytes 010 768 Bytes 4-2 XRS1-0 011 1024 Bytes 100 1792 Bytes 101 2048 Bytes (default configuration ...

Page 29

Power Monitor Description Figure 14. Power Monitor Block Diagram 4182O–CAN–09/08 The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power sup- ply falls below a ...

Page 30

Figure 15. Power Fail Detect Vcc Reset Vcc AT89C51CC03 30 When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at ...

Page 31

Reset Introduction Reset Input 4182O–CAN–09/08 The reset sources are : Power Management, Hardware Watchdog, PCA Watchdog and Reset input. Figure 16. Reset Schematic Power Monitor Hardware Watchdog PCA Watchdog RST The Reset input can be used to force a reset ...

Page 32

Reset Output AT89C51CC03 32 As detailed in Section “Watchdog Timer”, page 81, the WDT generates a 96-clock period pulse on the RST pin. In order to properly propagate this pulse to the rest of the application in case of external ...

Page 33

Power Management Introduction Idle Mode Entering Idle Mode Exiting Idle Mode Power-Down Mode 4182O–CAN–09/08 Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and the Power-Down mode. These modes are detailed in the following sections. In addition ...

Page 34

Entering Power-Down Mode Exiting Power-Down Mode Figure 19. Power-Down Exit Waveform Using INT1:0# INT1:0# OSC Active phase AT89C51CC03 34 To enter Power-Down mode, set PD bit in PCON register. The AT89C51CC03 enters the Power-Down mode upon execution of the instruction ...

Page 35

Table 9. Pin Conditions in Special Operating Modes Mode Port 0 Port 1 Reset Floating High Idle (internal Data Data code) Idle (external Floating Data code) Power- Down(inter Data Data nal code) Power- Down Floating Data (external code) AT89C51CC03 ...

Page 36

Registers AT89C51CC03 36 Table 10. PCON Register PCON (S87:h) Power configuration Register Bit Bit Number Mnemonic Description Reserved 7-4 - The value read from these bits is indeterminate. Do not set these bits. General ...

Page 37

EEPROM Data Memory Write Data in the Column Latches Programming Read Data 4182O–CAN–09/08 The 2-Kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/ERAM memory space and is selected by setting control bits in the ...

Page 38

Examples AT89C51CC03 38 ;*F*************************************************************************;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: MOV EECON, #02h; map EEPROM in XRAM ...

Page 39

Registers 4182O–CAN–09/08 Table 11. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch command bits 7-4 EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the programming. Reserved ...

Page 40

Program/Code Memory AT89C51CC03 40 The AT89C51CC03 implement 64K Bytes of on-chip program/code memory. Figure 20 shows the partitioning of internal and external program/code memory spaces depending on the product. The Flash memory increases EPROM and ROM functionality by in-circuit electrical ...

Page 41

External Code Memory Access Memory Interface External Bus Cycles 4182O–CAN–09/08 The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN#, and ALE). Figure 21 shows the structure of the ...

Page 42

Figure 22. External Code Fetch Waveforms CPU Clock ALE PSEN# P0 D7:0 P2 PCH Flash Memory Architecture Figure 23. Flash Memory Architecture with ENBOOT=1 (boot mode) Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) AT89C51CC03 42 ...

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Figure 24. Flash Memory Architecture with ENBOOT=0 (user modemode) Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) 4182O–CAN–09/08 FFFFh 64K Bytes F800h FM0 0000h Memory space not accessible AT89C51CC03 FFFFh 2K Bytes Flash memory boot space ...

Page 44

FM0 Memory Architecture User Space Extra Row (XRow) Hardware security Byte (HSB) Column Latches Cross Flash Memory Access Description AT89C51CC03 44 The Flash memory is made blocks (see Figure 23): • The memory array (user space) 64K ...

Page 45

Cross Flash Memory Access Action Read Load column latch FM0 (user Flash) Write Read Load column latch FM1 (boot Flash) Write Read External Load column latch memory Write (a) Depend upon general lock bit configuration. AT89C51CC03 ...

Page 46

Overview of FM0 Operations Flash Registers (SFR) FCON Register AT89C51CC03 46 The CPU interfaces to the flash memory through the FCON register, AUXR1 register and FSTA register. These registers are used to map the column latches, HSB, extra row and ...

Page 47

FSTA Register Mapping of the Memory Space By default, the user space is accessed by MOVC A, @DPTR instruction for read only. Launching Programming 4182O–CAN–09/08 Table 14. FSTA Register FSTA Register (S:D3h) Flash Status Register Bit Bit ...

Page 48

Status of the Flash Memory Selecting FM1 Loading the Column Latches AT89C51CC03 48 Table 16. Programming Spaces Write to FCON FPL3:0 FPS User Extra Row Hardware 5 X Security A X Byte ...

Page 49

The page address of the last address loaded in the column latches will be used for the whole page. When programming is launched, an automatic erase of the locations loaded in the col- umn latches is first performed, ...

Page 50

Programming the Flash Spaces User Extra Row AT89C51CC03 50 Figure 25. Column Latches Loading Procedure Note: The last page address used when loading the column latch is the one used to select the page programming address. The following procedure is ...

Page 51

Hardware Security Byte 4182O–CAN–09/08 Figure 26. Flash and Extra Row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 27: • Set FPS and map Hardware byte (FCON = 0x0C) • Save and ...

Page 52

Reset the Column Latches Error Reports Flash Programming Sequence Errors AT89C51CC03 52 Figure 27. Hardware Programming Procedure Flash Spaces Programming Save and Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX ...

Page 53

Power Down Request Reading the Flash Spaces User Extra Row Hardware Security Byte Flash Protection from Parallel Programming 4182O–CAN–09/08 Before entering in Power Down (Set bit PD in PCON register) the user should check that no write sequence is in ...

Page 54

AT89C51CC03 54 Table 17. Program Lock Bit Program Lock Bits Security LB0 LB1 LB2 level Protection Description program lock features enabled. MOVC instruction executed from external program memory are disabled from fetching code bytes from ...

Page 55

Operation Cross Memory Access Table 18. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write External memory Read Write or Code Roll Over Note: 1. RWW: Read While Write 4182O–CAN–09/08 Space addressable in read ...

Page 56

Sharing Instructions AT89C51CC03 56 Table 19. Instructions shared XRAM EEPROM Action RAM ERAM DATA Read MOV MOVX MOVX Write MOV MOVX MOVX Note using Column Latch Table 20. Read MOVX A, @DPTR EEE bit in FPS in ...

Page 57

Table 22. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 From FM0 From FM1 (ENBOOT = External code : X 0 EA=0 ...

Page 58

... This In-System Programming (ISP) allows code modification over the total lifetime of the product. Besides the default Boot loader Atmel provide to the customer also all the needed Appli- cation-Programming-Interfaces (API) which are needed for the ISP. The API are located also in the Boot memory. ...

Page 59

Hardware Boot Process 4182O–CAN–09/08 Boot Loader Jump Bit (BLJB): - This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - ...

Page 60

... Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made by functions. All these APIs are describe in an documentation: "In-System Programing: Flash Library for AT89C51CC03" available on the Atmel web site. Table 23. XROW Mapping Description Copy of the Manufacturer Code ...

Page 61

Hardware Security Byte 4182O–CAN–09/08 Table 24. Hardware Security Byte X2B BLJB - Bit Bit Number Mnemonic Description X2 Bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 mode. ...

Page 62

Serial I/O Port Figure 31. Serial I/O Port Block Diagram TXD RXD Framing Error Detection Figure 32. Framing Error Block Diagram AT89C51CC03 62 The AT89C51CC03 I/O serial port is compatible with the I/O serial port in the 80C52. It provides ...

Page 63

Automatic Address Recognition 4182O–CAN–09/08 valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the stop bit instead of the last data bit (See Figure 33. and Figure 34.). Figure 33. UART Timing ...

Page 64

Given Address Broadcast Address AT89C51CC03 64 Each device has an individual address that is specified in the SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The ...

Page 65

Registers 4182O–CAN–09/08 For slaves A and B, bit don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A ...

Page 66

AT89C51CC03 66 Table 26. SADEN Register SADEN (S:B9h) Slave Address Mask Register – – – Bit Bit Number Mnemonic Description 7-0 Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 27. ...

Page 67

Table 29. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 – Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 68

Timers/Counters Timer/Counter Operations Timer 0 AT89C51CC03 68 The AT89C51CC03 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an ...

Page 69

Mode 0 (13-bit Timer) Figure 35. Timer/Counter Mode 0 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 1 (16-bit Timer) Figure 36. Timer/Counter x ...

Page 70

Mode 2 (8-bit Timer with Auto- Reload) Figure 37. Timer/Counter Mode 2 See the “Clock” section FTx ÷ 6 CLOCK Tx C/Tx# TMOD reg INTx# GATEx TMOD reg Mode 3 (Two 8-bit Timers) ...

Page 71

Timer 1 Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) 4182O–CAN–09/08 Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. The fol- lowing ...

Page 72

Interrupt Registers AT89C51CC03 72 Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer interrupt routine. Interrupts are ...

Page 73

Table 31. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control Bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. Set ...

Page 74

AT89C51CC03 74 Table 32. TH0 Register TH0 (S:8Ch) Timer 0 High Byte Register – – – Bit Bit Number Mnemonic Description 7:0 High Byte of Timer 0. Reset Value = 0000 0000b Table 33. TL0 Register TL0 ...

Page 75

Table 35. TL1 Register TL1 (S:8Bh) Timer 1 Low Byte Register – – – Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 1. Reset Value = 0000 0000b AT89C51CC03 – ...

Page 76

Timer 2 Auto-Reload Mode Figure 40. Auto-Reload Mode Up/Down Counter see section “Clock” FT2 CLOCK T2 AT89C51CC03 76 The AT89C51CC03 timer 2 is compatible with timer 2 in the 80C52 16-bit timer/counter: the count is maintained by ...

Page 77

Programmable Clock- Output Figure 41. Clock-Out Mode FT2 CLOCK T2 T2EX 4182O–CAN–09/08 In clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (See Figure 41). The input clock increments TL2 at frequency F repeatedly counts to overflow ...

Page 78

Registers AT89C51CC03 78 Table 36. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 ...

Page 79

Table 37. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 80

AT89C51CC03 80 Table 39. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description 7-0 Low Byte of Timer 2. Reset Value = 0000 0000b Not bit addressable Table 40. ...

Page 81

Watchdog Timer Figure 42. Watchdog Timer RESET Fwd Clock - 4182O–CAN–09/08 AT89C51CC03 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has elapsed. ...

Page 82

Watchdog Programming AT89C51CC03 82 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 42. Machine Cycle Count ...

Page 83

Watchdog Timer During Power-down Mode and Idle Register 4182O–CAN–09/08 In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting ...

Page 84

AT89C51CC03 84 Table 45. WDTRST Register WDTRST (S:A6h Write only) Watchdog Timer Enable Register – – – Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register is ...

Page 85

CAN Controller CAN Protocol Principles Message Formats Can Standard Frame Figure 43. CAN Standard Frames Data Frame Bus Idle 11-bit identifier SOF SOF ID10..0 Interframe Arbitration Space Remote Frame Bus Idle 11-bit identifier SOF SOF ID10..0 Interframe Arbitration Space 4182O–CAN–09/08 ...

Page 86

CAN Extended Frame Figure 44. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field ...

Page 87

... It is the time required for the logic to determine the bit level of a sampled bit. The Information processing Time begins at the sample point, is measured in TQ and is fixed for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, Phase Segment 2 minimum shall not be less than the Information processing Time ...

Page 88

Bit Shortening Synchronization Jump Width Programming the Sample Point Arbitration Errors Error at Message Level AT89C51CC03 88 If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be ...

Page 89

Error at Bit Level Error Signalling CAN Controller Description 4182O–CAN–09/08 fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". • ACK Errors As already mentioned frames received are acknowledged by all ...

Page 90

Figure 47. CAN Controller Block Diagram TxDC RxDC CAN Controller Mailbox and Registers Organization AT89C51CC03 90 Bit Error Timing Counter Logic Rec/Tec Page DPR(Mailbox + Registers) Register µC-Core Interface Interface Core Bus Control The pagination allows management of the 321 ...

Page 91

Figure 48. CAN Controller Memory Organization SFR’s General Control General Status General Interrupt Bit Timing - 1 Bit Timing - 2 Bit Timing - 3 Enable message object - 1 Enable message object - 2 Enable Interrupt Enable Interrupt message ...

Page 92

Working on Message Objects CAN Controller Management AT89C51CC03 92 The Page message object register (CANPAGE) is used to select one of the 15 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected ...

Page 93

Buffer Mode 4182O–CAN–09/08 Any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used up to 15. Each message object of the buffer must be initialized ...

Page 94

IT CAN Management Figure 50. CAN Controller Interrupt Structure CANGIE.5 ENRX RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 CERR i CANSTCH.2 FERR i CANSTCH.1 AERR i CANSTCH.0 OVRBUF CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 ...

Page 95

Enable General CAN IT in the interrupt system register, • Enable interrupt by message object, EICHi, • Enable interrupt on error, ENERCH. To enable an interrupt on general error: • Enable General CAN IT in the interrupt system ...

Page 96

Bit Timing and Baud Rate Figure 51. Sample And Transmission Point FCAN Prescaler BRP CLOCK AT89C51CC03 96 FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing ...

Page 97

Figure 52. General Structure of a Bit Period oscillator system clock data (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 4182O–CAN–09/08 1/ Fcan Bit Rate Prescaler Tscl one ...

Page 98

Fault Confinement ERRP = 1 BOFF = 0 AT89C51CC03 98 With respect to fault confinement, a unit may be in one of the three following status: • error active • error passive • bus off An error active unit takes ...

Page 99

Acceptance Filter 4182O–CAN–09/08 Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR ...

Page 100

Data and Remote Frame message object in transmission message object disabled message object in transmission message object in reception by CAN controller message object disabled 1 message object in u transmission message object disabled 0 c message object in 0 ...

Page 101

Time Trigger Communication (TTC) and Message Stamping Figure 55. Block Diagram of CAN Timer Fcan ÷ 6 CLOCK TXOK i CANSTCH.4 RXOK i CANSTCH.5 CANSTMPH and CANSTMPL 4182O–CAN–09/08 The AT89C51CC03 has a programmable 16-bit Timer (CANTIMH and CANTIML) for message ...

Page 102

CAN Autobaud and Listening Mode Routines Examples AT89C51CC03 102 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the ...

Page 103

Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11-bit identi- fier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this ...

Page 104

AT89C51CC03 104 4. Interrupt routine // Save the current CANPAGE // Find the first message object which generate an interrupt in CANSIT1 and CANSIT2 // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of ...

Page 105

CAN SFR’s Table 47. CAN SFR’s With Reset Values (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 00xx xx00 00xx ...

Page 106

Registers AT89C51CC03 106 Table 48. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC SYNCTTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control ...

Page 107

Table 49. CANGSTA Register CANGSTA (S:AAh Read Only) CAN General Status Register OVFG - Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. ...

Page 108

AT89C51CC03 108 Table 50. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General Interrupt Flag This status bit is the image of all the CAN controller interrupts sent to the ...

Page 109

Table 51. CANTEC Register CANTEC (S:9Ch Read Only) CAN Transmit Error Counter TEC7 TEC6 TEC5 Bit Number Bit Mnemonic Description Transmit Error Counter 7-0 TEC7:0 see Figure 53 Reset Value = 00h Table 52. CANREC Register ...

Page 110

AT89C51CC03 110 Table 53. CANGIE Register CANGIE (S:C1h) CAN General Interrupt Enable ENRX Bit Number Bit Mnemonic Description Reserved 7-6 - The values read from these bits are indeterminate. Do not set these bits. Enable ...

Page 111

Table 54. CANEN1 Register CANEN1 (S:CEh Read Only) CAN Enable Message Object Registers ENCH14 ENCH13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set ...

Page 112

AT89C51CC03 112 Table 56. CANSIT1 Register CANSIT1 (S:BAh Read Only) CAN Status Interrupt Message Object Registers SIT14 SIT13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do ...

Page 113

Table 58. CANIE1 Register CANIE1 (S:C2h) CAN Enable Interrupt Message Object Registers IECH14 IECH13 Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this ...

Page 114

AT89C51CC03 114 Table 60. CANBT1 Register CANBT1 (S:B4h) CAN Bit Timing Registers BRP 5 BRP 4 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...

Page 115

Table 61. CANBT2 Register CANBT2 (S:B5h) CAN Bit Timing Registers SJW 1 SJW 0 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this ...

Page 116

AT89C51CC03 116 Table 62. CANBT3 Register CANBT3 (S:B6h) CAN Bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...

Page 117

Table 63. CANPAGE Register CANPAGE (S:B1h) CAN Message Object Page Register CHNB 3 CHNB 2 CHNB 1 Bit Number Bit Mnemonic Description Selection of Message Object Number 7-4 CHNB3:0 The available numbers are ...

Page 118

AT89C51CC03 118 Table 65. CANSTCH Register CANSTCH (S:B2h) CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. Whatever the frame ...

Page 119

Table 66. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) CAN Identifier Tag Registers IDT 10 IDT 9 IDT 8 Bit Number Bit Mnemonic Description IDentifier tag value 7-0 IDT10:3 See ...

Page 120

AT89C51CC03 120 Table 69. CANIDT4 Register for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these ...

Page 121

Table 72. CANIDT3 Register for V2.0 part B CANIDT3 for V2.0 part B (S:BEh) CAN Identifier Tag Registers IDT 12 IDT 11 IDT 10 Bit Number Bit Mnemonic Description IDentifier Tag Value 7-0 IDT12:5 See ...

Page 122

AT89C51CC03 122 Table 75. CANIDM2 Register for V2.0 part A CANIDM2 for V2.0 part A (S:C5h) CAN Identifier Mask Registers IDMSK 2 IDMSK 1 IDMSK 0 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - ...

Page 123

Table 77. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers Bit Number Bit Mnemonic Description Reserved 7-3 - The values read from these bits ...

Page 124

AT89C51CC03 124 Table 79. CANIDM2 Register for V2.0 part B CANIDM2 for V2.0 part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 Bit Number Bit Mnemonic Description IDentifier Mask Value ...

Page 125

Table 81. CANIDM4 Register for V2.0 part B CANIDM4 for V2.0 part B (S:C7h) CAN Identifier Mask Registers IDMSK 4 IDMSK 3 IDMSK 2 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...

Page 126

AT89C51CC03 126 Table 83. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main ...

Page 127

Table 86. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High TIMSTMP TIMSTMP TIMSTMP Bit Number Bit Mnemonic Description TIMSTMP15: High byte of Time Stamp 7-0 8 See Figure 55. No default ...

Page 128

AT89C51CC03 128 Table 89. CANTTCL Register CANTTCL (S:A4h Read Only) CAN TTC Timer Low TIMTTC 7 TIMTTC 6 TIMTTC 5 Bit Number Bit Mnemonic Description Low byte of TTC Timer 7-0 TIMTTC7:0 See Figure 55. Reset Value ...

Page 129

Serial Port Interface (SPI) Features Signal Description Master Output Slave Input (MOSI) Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) 4182O–CAN–09/08 The Serial Peripheral Interface Module (SPI) allows full-duplex, synchronous, serial communication between the MCU and ...

Page 130

Baud Rate AT89C51CC03 130 In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSCR) to prevent multiple masters from driving MOSI and SCK (see Error conditions). A high ...

Page 131

Functional Description Figure 58. SPI Module Block Diagram SPSCR SPIF - OVR SPI Control SPCON SPR2 SPEN SSDIS Operating Modes 4182O–CAN–09/08 Figure 58 shows a detailed structure of the SPI Module. Internal Bus MODF SPTE UARTM SPTEIE MODFIE MSTR CPOL ...

Page 132

Master Mode Slave Mode Transmission Formats AT89C51CC03 132 When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex ...

Page 133

Figure 60. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point Figure 61. Data Transmission Format (CPHA = 1) ...

Page 134

Figure 63. Queuing Transmission In Master Mode SCK MSB MOSI MSB MISO Data Byte 1 BYTE 1 under transmission SPTE AT89C51CC03 134 When a transmission is in progress a new data can be queued ...

Page 135

Error Conditions Mode Fault Error (MODF) 4182O–CAN–09/08 The following flags in the SPSCR register indicate the SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the ...

Page 136

OverRun Condition Interrupts AT89C51CC03 136 Figure 65. Mode Fault Conditions in Slave Mode 0 SCK cycle # 1 SCK z 0 (from master) 1 MOSI z (from master MISO MSB z (from slave (slave) ...

Page 137

Registers Serial Peripheral Control Register (SPCON) 4182O–CAN–09/08 Figure 66. SPI Interrupt Requests Generation SPIF SPTEIE SPTE MODFIE MODF Three registers in the SPI module provide control, status and data storage functions. These registers are describe in the following paragraphs. • ...

Page 138

Serial Peripheral Status Register and Control (SPSCR) AT89C51CC03 138 Bit Number Bit Mnemonic Description Clock Polarity 3 CPOL Cleared to have the SCK set to ’0’ in idle state. Set to have the SCK set to ’1’ in idle state. ...

Page 139

Serial Peripheral DATa Register (SPDAT) 4182O–CAN–09/08 Bit Bit Number Mnemonic Description Mode Fault - Set by hardware to indicate that the SS pin is in inappropriate logic level (in both master and slave modes). - Cleared by hardware when reading ...

Page 140

AT89C51CC03 140 SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: • Do not change ...

Page 141

Programmable Counter Array (PCA) PCA Timer 4182O–CAN–09/08 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which serves ...

Page 142

Figure 67. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle PCA Modules AT89C51CC03 142 CIDL WDTE CPS1 CPS0 CF CR CCF4 CCF3 CCF2 CCF1 CCF0 The CMOD register includes three additional bits associated with the PCA. • The CIDL bit ...

Page 143

PCA Interrupt Figure 68. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 Module 2 Module 3 Module 4 PCA Capture Mode 4182O–CAN–09/08 Each module in the PCA has a special function register associated with it (CCAPM0 for module 0 ...

Page 144

Figure 69. PCA Capture Mode CEXn 16-bit Software Timer Mode Figure 70. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to ...

Page 145

High Speed Output Mode Figure 71. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode 4182O–CAN–09/08 In this mode the CEX output (on port 1) associated with the PCA module ...

Page 146

Figure 72. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) PCA WatchDog Timer AT89C51CC03 146 CCAPnH CCAPnL 8-Bit Comparator ECOMn PWMn CCAPMn.6 CCAPMn.1 An on-board WatchDog timer is available with ...

Page 147

PCA Registers 4182O–CAN–09/08 Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL WDTE - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. ...

Page 148

AT89C51CC03 148 Table 96. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Bit Number Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA ...

Page 149

Table 97. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) CCAP2H (S:FCh) CCAP3H (S:FDh) CCAP4H (S:FEh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 Bit Bit Number Mnemonic Description CCAPnH 7:0 High ...

Page 150

AT89C51CC03 150 Table 99. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) CCAPM2 (S:DCh) CCAPM3 (S:DDh) CCAPM4 (S:DEh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Bit Number Mnemonic Description Reserved 7 - The Value read ...

Page 151

Table 100. CH Register CH (S:F9h) PCA Counter Register High Value Bit Bit Number Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 101. ...

Page 152

Analog-to-Digital Converter (ADC) Features ADC Port1 I/O Functions AT89C51CC03 152 This section describes the on-chip 10 bit analog-to-digital converter of the AT89C51CC03. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows ...

Page 153

Figure 73. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 74. Timing Diagram CLK ADEN T SETUP ADSST ADEOC Note: Tsetup min = ...

Page 154

ADC Converter Operation Voltage Conversion Clock Selection AT89C51CC03 154 A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3). After completion of the A/D conversion, the ADSST bit is cleared by hardware. The end-of-conversion flag ADEOC (ADCON.4) ...

Page 155

Figure 75. A/D Converter Clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode IT ADC Management Routines examples 4182O–CAN–09/08 Prescaler ADCLK ÷ 2 When the ADC is not used possible to set it in standby mode by ...

Page 156

AT89C51CC03 156 EADC = 1 // clear the field SCH[2:0] ADCON and = F8h // Select the channel ADCON | = channel // Start conversion in precision mode ADCON | = 48h Note: to enable the ADC interrupt ...

Page 157

Registers 4182O–CAN–09/08 Table 103. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 7-0 CH 0:7 Set to use P1.x as ADC input. Clear to use P1.x ...

Page 158

AT89C51CC03 158 Table 105. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved 7-5 - The value read from these bits are indeterminate. Do not set these bits. Clock Prescaler ...

Page 159

Bit Bit Number Mnemonic Description Reserved 7-2 - The value read from these bits are indeterminate. Do not set these bits. ADC result 1-0 ADAT1:0 bits 1-0 Reset Value = 00h AT89C51CC03 159 ...

Page 160

Interrupt System Introduction Figure 77. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:5 PCA TxD UART RxD Timer 2 TxDC CAN controller RxDC AIN1:0 Converter CAN Timer SPI Controller ...

Page 161

Each of the interrupt sources can be individually enabled or disabled by setting or clear- ing a bit in the Interrupt Enable register. This register also contains a global disable bit which must be cleared to disable all the ...

Page 162

Registers AT89C51CC03 162 Table 110. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If ...

Page 163

Table 111. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - ...

Page 164

AT89C51CC03 164 Table 112. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...

Page 165

Table 113. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 166

AT89C51CC03 166 Table 114. IPL0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...

Page 167

Table 115. IPH1 Register IPH1 (S:F7h) Interrupt High Priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 168

Electrical Characteristics Absolute Maximum Ratings Ambiant Temperature Under Bias industrial........................................................-40°C to 85° automotive..................................................-40°C to +125°C Voltage on V from V ......................................-0. Voltage on Any Pin from V ..................... -0. ...

Page 169

Table 116. DC Parameters in Standard Voltage (Continued) Symbol Parameter V Output High Voltage, ports and Output High Voltage, port 0, ALE, PSEN OH1 R RST Pulldown Resistor RST I Logical 0 Input Current ...

Page 170

Power Fail Detect at Ambiant Temperatures AT89C51CC03 170 (1) VPFDP VPFDM 2.5V typ 2.35V typ Note: 1. Threshold Voltage for PFD Release 2. Threshold Voltage for PFD Activation Figure 78. I Test Condition, Active Mode ...

Page 171

DC Parameters for A/D Converter AC Parameters Explanation of the AC Symbols 4182O–CAN–09/08 Figure 81. Clock Signal Waveform for I V -0.5V CC 0.45V T CHCL T CLCH Table 117. DC Parameters for AD Converter in Precision Conversion Symbol Parameter ...

Page 172

External Program Memory Characteristics AT89C51CC03 172 Table 118. Symbol Description Symbol Parameter T Oscillator clock period T ALE pulse width LHLL T Address Valid to ALE AVLL T Address Hold After ALE LLAX T ALE to Valid Instruction In LLIV ...

Page 173

External Program Memory Read Cycle ALE PSEN PORT 0 INSTR IN ADDRESS PORT 2 OR SFR-P2 4182O–CAN–09/08 Table 120. AC Parameters for a Variable Clock Symbol Type T Min LHLL T Min AVLL T Min LLAX T Max LLIV T ...

Page 174

External Data Memory Characteristics AT89C51CC03 174 Table 121. Symbol Description Symbol Parameter T RD Pulse Width RLRH T WR Pulse Width WLWH Valid Data In RLDV T Data Hold After RD RHDX T Data Float After RD ...

Page 175

Table 123. AC Parameters for a Variable Clock Symbol Type T Min RLRH T Min WLWH T Max RLDV T Min RHDX T Max RHDZ T Max LLDV T Max AVDV T Min LLWL T Max LLWL T Min ...

Page 176

External Data Memory Write Cycle ALE PSEN WR PORT 0 ADDRESS PORT 2 OR SFR-P2 External Data Memory Read Cycle ALE PSEN RD PORT 0 ADDRESS PORT 2 OR SFR-P2 Serial Port Timing – Shift Register Mode AT89C51CC03 176 T ...

Page 177

Shift Register Timing Waveforms INSTRUCTION ALE CLOCK OUTPUT DATA WRITE to SBUF INPUT DATA External Clock Drive Characteristics (XTAL1) 4182O–CAN–09/08 Table 125. AC Parameters for a Fix Clock ( MHz) Symbol T XLXL T QVHX T XHQX T ...

Page 178

External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms AT89C51CC03 178 V -0.5V CC 0.7V CC 0.2V -0.1 0.45V CC T CHCL V -0.5V CC INPUT/OUTPUT 0.45V AC inputs during testing are driven at V Timing measurement are made ...

Page 179

Clock Waveforms STATE4 INTERNAL CLOCK P1 P2 XTAL2 ALE EXTERNAL PROGRAM MEMORY FETCH PSEN P0 DATA SAMPLED FLOAT P2 (EXT) READ CYCLE WRITE CYCLE PORT OPERATION MOV PORT SRC MOV DEST P0 MOV DEST ...

Page 180

Flash/EEPROM Memory A/D Converter AT89C51CC03 180 Table 128. Timing Symbol Definitions Signals S (Hardware PSEN#,EA condition) R RST B FBUSY flag Table 129. Memory AC Timing VDD = 3V to 5.5V -40 to +85°C Symbol Parameter T Input ...

Page 181

Timings Table 1. SPI Interface Master AC Timing V = 2 -40 to +85° Symbol T Clock Period CHCH T Clock High Time CHCX T Clock Low Time CLCX ...

Page 182

Waveforms (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) SS (input) SCK (SSCPOL= 0) (input) SCK (SSCPOL= 1) (input) MISO (output) MOSI (input) AT89C51CC03 182 Figure 84. SPI Slave Waveforms (SSCPHA SLCH ...

Page 183

SS (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI (input) MISO (output) SS (output) SCK (SSCPOL= 0) (output) SCK (SSCPOL= 1) (output) MOSI (input) MISO (output) 4182O–CAN–09/08 Figure 86. SPI Master Waveforms (SSCPHA CHCH T T ...

Page 184

... Table 131. Possible Order Entries Boot Part Number Loader AT89C51CC03U-7CTIM AT89C51CC03U-RLTIM AT89C51CC03U-SLSIM AT89C51CC03C-7CTIM AT89C51CC03C-RLTIM AT89C51CC03C-SLSIM AT89C51CC03U-RDTIM AT89C51CC03U-S3SIM AT89C51CC03C-RDTIM AT89C51CC03C-S3SIM AT89C51CC03UA-RLTUM UART AT89C51CC03UA-SLSUM UART AT89C51CC03CA-RLTUM CAN AT89C51CC03CA-SLSUM CAN AT89C51CC03UA-RDTUM UART AT89C51CC03UA-S3SUM UART AT89C51CC03CA-S3SUM CAN AT89C51CC03CA-RDTUM CAN AT89C51CC03 184 Temperature Range Quality Grade OBSOLETE -40 to +85° ...

Page 185

Package Drawings VQFP44 4182O–CAN–09/08 AT89C51CC03 185 ...

Page 186

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

Page 187

PLCC44 4182O–CAN–09/08 AT89C51CC03 187 ...

Page 188

STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm ...

Page 189

VQFP64 4182O–CAN–09/08 AT89C51CC03 189 ...

Page 190

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

Page 191

PLCC52 4182O–CAN–09/08 AT89C51CC03 191 ...

Page 192

Datasheet Change Log Changes from 4182B - 09/03 to 4182C 12/03 Changes from 4182C - 12/03 to 4182D 01/04 Changes from 4182D - 01/04 to 4182E 05/04 Changes from 4182E - 05/04 to 4182F 10/04 Changes from 4182F - 10/04 ...

Page 193

Changes from 4182N 03/08 to 4182O 09/08 4182O–CAN–09/08 1. Correction to SPDT register address Table 94 on page 139. AT89C51CC03 193 ...

Page 194

Table of Contents Features ................................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................... 2 Pin Configuration ................................................................................. 3 I/O Configurations................................................................................................. 7 Port 1, Port 3 and Port 4 ....................................................................................... 7 Port 0 and Port 2................................................................................................... 8 Read-Modify-Write Instructions ............................................................................ 9 Quasi-Bidirectional ...

Page 195

Registers............................................................................................................. 39 Program/Code Memory ...................................................................... 40 External Code Memory Access .......................................................................... 41 Flash Memory Architecture................................................................................. 42 Overview of FM0 Operations .............................................................................. 46 Operation Cross Memory Access ..................................................... 55 Sharing Instructions ........................................................................... 56 In-System Programming (ISP) ........................................................... 58 Flash Programming and ...

Page 196

IT CAN Management .......................................................................................... 94 Bit Timing and Baud Rate ................................................................................... 96 Fault Confinement .............................................................................................. 98 Acceptance Filter ................................................................................................ 99 Data and Remote Frame .................................................................................. 100 Time Trigger Communication (TTC) and Message Stamping .......................... 101 CAN Autobaud and Listening Mode ...

Page 197

DC Parameters for A/D Converter .................................................................... 171 AC Parameters .................................................................................................171 Timings ............................................................................................................. 181 Ordering Information ........................................................................ 184 Package Drawings ............................................................................ 185 VQFP44 ............................................................................................................ 185 PLCC44 ............................................................................................................ 187 VQFP64 ............................................................................................................ 189 PLCC52 ............................................................................................................ 191 Datasheet Change Log ..................................................................... 192 Changes from ...

Page 198

... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise,to anyintellectu- alproperty right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWAR- RANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICU- LARPURPOSE, OR NON-INFRINGEMENT ...

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