ATA6602-PLQW ATMEL [ATMEL Corporation], ATA6602-PLQW Datasheet - Page 246

• Manufacturer Part Number: ATA6602-PLQW
• Description: Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
• Manufacturer: ATMEL [ATMEL Corporation]

4.19.8.2
246
ATA6602/ATA6603
Master Receiver Mode
Figure 4-89. Formats and States in the Master Transmitter Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(Slave see
be transmitted. The format of the following address packet determines whether Master Transmit-
ter or Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if
SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section
assume that the prescaler bits are zero or are masked to zero.
Successfull
transmission
to a slave
receiver
Next transfer
started with a
repeated start
condition
Not acknowledge
received after the
slave address
Not acknowledge
received after a data
byte
Arbitration lost in slave
address or data byte
Arbitration lost and
addressed as slave
Figure 4-90 on page
From master to slave
From slave to master
$08
S
SLA
247). In order to enter a Master mode, a START condition must
W
MT
A or A
DATA
$18
$20
$38
$68
A
A
A
$78
Other master
Other master
continues
continues
n
P
$B0
DATA
A
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
A or A
$28
$30
$38
To corresponding
states in slave mode
A
A
Other master
continues
$10
P
R
P
S
SLA
4921C–AUTO–01/07
W
R
MR