AD8117_07 AD [Analog Devices], AD8117_07 Datasheet - Page 13

• Manufacturer Part Number: AD8117_07
• Manufacturer: AD [Analog Devices]

TRUTH TABLE AND LOGIC DIAGRAM
Table 9. Operation Truth Table
WE
X
0
1
0
1
1
1
2
3
D0…D5: data bits.
Data
A0…A4: address bits.
i
: serial data.
UPDATE
X
X
X
X
0
X
X
CLK
X
X
X
X
DATA
INPUT
X
D0…D5
Data
D0…D5
A0…A4
X
X
i
2
3
1
1
DATA
OUTPUT
X
NA in
parallel
mode
Data
NA in
parallel
mode
NA in
parallel
mode
X
i-192
Rev. A | Page 13 of 36
RESET
0
1
1
1
1
1
SER/PAR
X
0
0
1
X
1
Operation/Comment
Asynchronous reset. All outputs are
disabled. Remainder of logic in 192-bit shift
register is unchanged.
Broadcast. The data on parallel lines D0 to
D5 are loaded into all 32 output address
locations of the 192-bit shift register.
Serial mode. The data on the serial DATA IN
line is loaded into the serial register. The first
bit clocked into the serial register appears
at DATA OUT 192 clock cycles later.
Parallel programming mode. The data on
parallel lines D0 to D5 are loaded into the
shift register location addressed by A0 to A4.
Switch matrix update. Data in the 192-bit
shift register transfers into the parallel
latches that control the switch array.
No change in logic.
AD8117/AD8118