MC44S803EP FREESCALE [Freescale Semiconductor, Inc], MC44S803EP Datasheet - Page 10

• Manufacturer Part Number: MC44S803EP
• Description: Low Power CMOS Broadband Tuner
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Table 10. SPI Interface Bus Specifications
SPI TIMING
polarity combinations. Freescale microcontrollers should be
configured using CPOL = 0 and clock phase, CPHA = 0. See
the product documentation for more information. A clock
polarity of 0 simply means that the slave samples MOSI line
and master samples MISO line on the rising edge of the
SCLK. A clock phase of 0 means that the first edge on the
SCLK line is used to clock the first data bit of the slave into
the master and the first data bit of the master into the slave.
MOSI and MISO transition on the falling edge of SCLK.
MC44S803
10
Low Level Output Voltage
High Level Input Voltage
Low Level Input Voltage
Absolute Maximum Input Voltage
SCLK Frequency
Data to Clock Set Up Time
Clock Pulse Width High
Clock Pulse Width Low
Leading, SS Falling to SCK Rising
Trailing, SCK Falling to SS Rising
SS Pulse Width High
1. Unless otherwise noted; V
See Figure 5 for timing references.
SPI buses can have one of four serial clock phase and
Sample Input
MOSI/MISO
SCLK
MOSI
MISO
SS
Characteristic
MSB:R19
MSB:D19
DD
(1)
= 3.3 Vdc, V
t
L
R18
D19
There is a maximum of 20 data bits, the rest are fixed
SS
t
CS
= GND = 0 Vdc, 0 < T
DIGITAL INTERFACE TIMING
Figure 5. SPI Timing Diagram
t
CWH
Symbol
f
t
t
t
V
SCLK
CWH
V
V
CWL
V
t
SSH
CS
t
t
OL
IH
IN
L
T
IL
R0
D1
A
< 85°C.
an external resistor. This allows multiple tuners to share the
same MISO line. The output from the MISO line can be
disabled by programming the SO bit of the Reset/SO Enable
register to 0. The MISO line is disabled at power up and reset.
out, the last three bits are fixed as 110.
they can be pulled up to 5.0 V if that is required to interface
with the microprocessor in a given application.
Min
2.3
—
—
—
—
—
—
—
—
—
—
A3
D0
The MISO pin has an open drain output that is pulled up by
The first bit out of MISO is repeated. For 24 bits clocked
The SPI/I
t
CWL
2
C interface lines are 5.0 V tolerant. Therefore,
A2
1
Typ
—
—
—
—
—
—
—
—
—
—
—
A1
1
LSB:A0
LSB:0
t
Freescale Semiconductor
SSH
t
Max
T
0.4
1.0
5.5
2.0
—
—
—
—
—
—
—
Units
MHz
ns
ns
ns
ns
ns
ns
V
V
V
V