MC44S803EP FREESCALE [Freescale Semiconductor, Inc], MC44S803EP Datasheet - Page 22

• Manufacturer Part Number: MC44S803EP
• Description: Low Power CMOS Broadband Tuner
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

provide automatic gain control (AGC) at the RF frequency.
The gain is varied with an external analog control voltage or
digitally via the interface bus using G5:G0. The Control bits
AGC An Dig bit determines if either analog or digital control
is controlling the AGC. There are two RF AGC control pins,
Mixer 1. To control this attenuator set At2, At1, and At0 as
shown in the Table 29 below. When the attenuator is set to a
value greater than 0 dB, the HL GR En bit and Atten En bit
is set high. This fixed gain adjustment has less of an affect on
noise figure than setting the LNA gain while still improving
distortion performance by limiting the levels hitting the first
mixer.
Table 29. Attenuator Control
Values range from 0 maximum gain to 63 minimum gain.
When using analog control the gain bits are not set. However,
the equivalent gain setting can be read back from the part.
The AGC Read En bit allows reading back of the RF AGC
setting. A 1 for this bit allows read back. This feature allows
the tuner to report back where the demodulator has set the
AGC gain. Note that when reading back this register, bits
G2:G0 are inverted.
MC44S803
22
MSB
LNA AGC REGISTER (CR-10)
R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9
LNA Bias
B2
Attenuation
0
The variable gain LNA (Low Noise Amplifier) is used to
There is a programmable attenuator between the LNA and
Digital control, bits G5:G0 are used to set the LNA gain.
1.1 dB
2.2 dB
3.2 dB
4.1 dB
4.8 dB
5.6 dB
6.3 dB
0 dB
B1
0
Table 30. RF AGC Control
Type of Control
At0
0
FEAGC_A
FEAGC_B
Digital
0
Attn En
0
1
1
1
1
1
1
1
1
0
AGC
HL GR En
Sel
X
1
0
0
0
1
1
1
1
1
1
1
AnDig
AGC
0
1
1
0
At 2
1
1
0
0
1
1
0
0
0
Gain Bits
G5:G0
Figure 23. LNA AGC Register Format
X:X
X:X
0
At1
1
1
1
1
0
0
0
0
0
At0
R8
0
1
0
1
0
1
0
1
0
At2 At1 G5
R7
0
Atten
R6
0
FEAGC_A and FEAGC_B. This facilitates having the tuner
connected to both analog and digital demodulators as found
in many set-top boxes, thus eliminating the need for an
external switch and its controls. The AGC Sel bit controls
which of these pins are used. Figure 23 shows the LNA AGC
register format.
LNA Bias bits, B2:B1, control the bias voltage in the LNA.
Table 31 shows how these bits should normally be
programmed. When reading the Regulator Test Data register,
LNA0 should be set to 0; otherwise, the LNA regulator test
will fail.
register to be read back during the next read from the IC. See
Read Operations Protocol section for more detail as to how
this is used. The default Data Address corresponds to the
LNA AGC register (CR 10).
DATA ADDRESS REGISTER (CR-11)
The LNA0 bit changes the dc output bias of the LNA. The
The Data Address Register sets the address of the data
R5
0
R4
G4
1
Normal AGC
R3
G3
1
Table 31. LNA Bias Control
G2
R2
LNA0
1
1
G1
R1
1
LNA Bias Bits
R0
G0
0
B2:B1
01
A3
1
Freescale Semiconductor
Address Bits
A2
0
A1
1
LSB
A0
0
Reset
State