MC44S803EP FREESCALE [Freescale Semiconductor, Inc], MC44S803EP Datasheet - Page 18

• Manufacturer Part Number: MC44S803EP
• Description: Low Power CMOS Broadband Tuner
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Low Power mode, which consumes half the power. For bits
LP3 and LP5 a 1 puts the amplifier in low power mode and a
0 puts it in nominal mode. For bit LPB0 a 0 puts Pre Amp 1
in a low power mode and a 1 puts it in nominal mode.
adjusting the power level of Mixer 1.
TEST REGISTER (CR-8)
directs test signals to the test pins.
RE – Regulator Test Enable: Enables the internal regulator
testing.
RL – Regulator Test Low: Determines if High Voltage Test =
0 or Low Voltage Test = 1 is tested when test is enabled.
Test bits: T6:T0 are always programmed to 0.
the test pin. The test pin has a user selectable function that is
used to monitor internal signals for test and development.
The TB3:TB0 and TA3:TA0 are used to select the function.
The Func Sel:AB bit is use to choose between function list
A (0) shown in Table 26 and function list B (1) shown in
Table 27. In normal operation, the Test Pin Func bits should
be set to the Disable mode, which is the reset state. Or, the
lock status could be routed to a microprocessor input for
monitoring. When the PLL lock detect logic signal is sent to
the test pin, a high state indicates PLL in lock.
test pin could then be used as a logic output to control an
external circuit. The state of the logic output would then be
changed by programming Gen Purp Out.
MC44S803
18
MSB
R18 R17 R16 R15 R14 R13 R12 R11 R10 R9
T6
0
The Power Adjust bits put their respective amplifiers into
Table 24 shows the settings for bits LPB2 and LBP1 for
The Test Register controls the various self test modes and
The Test Pin Function bits control which signal is sent to
The Gen Purp Out bit can be routed out the test pin. The
RL
0
Table 24. Mixer 1 Power Adjust
Mixer 1 Power
RE
0
Nominal
Middle
High
Low
T5
0
AB
0
LPB2
T4
0
0
0
1
1
T3
0
LBP1
0
1
0
1
Test
T2
0
Reset State
T1
0
Figure 17. Test Register Format
T0
0
GP TB3 TB2 TB1 TB0 TA3 TA2 TA1 TA0
R8
0
R7
1
Test Pin Func B
R6
0
Second IF output paths as shown in Table 25.
respectively. The peak detectors continue to record the peak
levels that they see until they are cleared and a new
measurement starts. To clear the detector, write a 1 to CLRF
or CLIF. Then write a 0 to CLRF or CLIF to bring the detector
out of the clear state. The detector will then operate in a “max
hold” mode where it continually records the highest peak that
it sees.
R5
1
The S1, Output Select, routes the signal to one of the two
CLRF and CLIF bits clear the RF and IF detector
R4
1
Table 25. Output Select
R3
1
Test Pin Func A
Analog Port
Digital Port
R2
State
0
R1
1
R0
1
S1
A3
0
1
1
Freescale Semiconductor
Address Bits
A2
0
Reset State
A1
0
LSB
A0
0
Reset
State